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參數(shù)資料
| 型號： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 61/109頁 |
| 文件大小： | 815K |
| 代理商： | L64381 |
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On-chip FIFOs
4-5
Transmit FIFO, the L64381 starts transmitting it after waiting the appro-
priate back-off time.
The Transmit FIFO asserts the BUF_AVAIL signal when it has at least as
many entries empty as specified in the Bus Transfer Size field (BUS).
This assertion signals the system that the L64381 can accommodate the
Bus Transfer Size amount of data into its Transmit FIFO. The system can,
at this point, write packet data into the FIFO. The Transmit FIFO initiates
a transmission on the Ethernet when it detects that the FIFO has at least
as many words as specified by the Transmit Threshold field, or the Trans-
mit FIFO detects an EOP stored in the FIFO. This situation can arise
when the Auto Pad feature is enabled for the port. The system must
guarantee that it can place into the FIFO data to be transmitted faster
than the time taken to transmit the data already in the FIFO.
The Transmit Threshold field provides a means of delaying the start of
transmission for slower systems. The Transmit FIFO sets the Transmit
FIFO Underrun Error bit in the Error Register if the FIFO detects an
underrun condition. The Transmit FIFO can never overrun, because the
Bus-In State Machine (described in Section 4.3.2, “Bus-In State
Machine”) does not request a write into the Transmit FIFO until it has
enough room for the data.
4.2.2
Receive FIFO
The Receive FIFO can be configured to initiate a bus transfer when the
Bus Transfer Size threshold has been met, or if the Receive FIFO detects
an EOP stored in the FIFO. This situation can arise when the packet size
is not a multiple of the Bus Transfer Size, or the packet is a runt packet.
The Receive FIFO initiates this transfer by setting the PKT_AVAIL signal.
This threshold can be programmed to be 4, 8, or 16 words. A threshold
setting of four words allows transmission of the packet with minimal
latency, while a setting of 16 words allows greater bus bandwidth (since
fewer idle cycles need to be inserted between transfers). The Receive
FIFO sets the Receive FIFO Overrun Error bit in the Error register if the
FIFO detects an overrun condition. The Receive FIFO can never under-
run, since the Bus-Out State Machine (4.3.1, “Bus-Out State Machine,”)
does not request a read from the Receive FIFO until it has enough data
in the FIFO.
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