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| 型號： | IDT88K8483BRI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 92/162頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI-4 EXCHANGE 3PORT 672-BGA |
| 標準包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88K8483BRI |
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October 20, 2006
IDT IDT88K8483
SPI-4 Ingress Port Buffer Structure
Each SPI-4 physical port in the ingress direction has 32 port buffers of 128 bytes as shown in Figure 7 SPI-4 Ingress Port Buffer Structure
. The buffers can be concatenated so that data flows from one FIFO into the next.
Figure 7 SPI-4 Ingress Port Buffer Structure
Flow Control
SPI-4 Ingress Flow Control
There are 3 main parameters for configuring the SPI-4 ingress flow control:
- Maximum number of segments per LID is configured in M field in the PFP Buffer Segment Assign Table (p. 120)
- Starving Free segments per LID is configured in THR_STARV field in the PFP Buffer Segment Assign Table (p. 120)
- Hungry Free segments per LID is configured in THR_HUNG field in the PFP Buffer Segment Assign Table (p. 120)
SPI-4 ingress flow control is described in greater detail in PFP Flow Control (p. 53)
SPI-4 Egress Flow Control
There are three LID status modes in the SPI-4 egress interface: starving, hungry and satisfied. In normal operation the SPI-4 egress interface is
receiving starving status from the adjacent device through the status bus, so the LID status is starving, and the LID data is scheduled out in round
robin. When the SPI-4 egress interface starts receiving hungry status from the adjacent device, the LID status is changed to hungry, and the LID data
is scheduled out in round robin. When the SPI-4 egress interface starts receiving satisfied status from the adjacent device, the LID status is changed
to satisfied, and the LID data is not scheduled out.
Each SPI-4 interface has four SPI-4 calendars: two for ingress and two for egress. Only one calendar in each direction is active in a specific time.
There are 64 LIDs per PFP, and each calendar has maximum of 256 entries. Each calendar entry can be assign to a specific LID as shown in Figure
. According to the calendar order, the LIDs with starving status are scheduled in a round robin fashion
with high priority, and the LIDs with hungry status are scheduled in a round robin fashion with low priority. All the LIDs with the starving status are
scheduled first. The LIDs with the hungry status are scheduled only when there are no LIDs with starving status.
The LID status mode in the SPI-4 egress interface (status or credit mode) is configured by CREDIT_EN field in the PFP Flow Control Register
(p. 125). If status mode is used (CREDIT_EN=0), then data is sent out until the LID status is changed (starving / hungry / satisfied).
If credit mode is used (CREDIT_EN=1), then when the credit is one, the device sends out one data burst, clears to zero the credit, and then waits
for another credit from the SPI-4 interface status bus before issuing another LID burst. In credit mode, when the SPI-4 egress interface receives
starving status or hungry status from the adjacent device through the status bus, it sets the LID credit to one. When the SPI-4 egress interface
receives satisfied status from the adjacent device, it clears the LID credit to zero.
Buffer 30
Buffer 1
Buffer 0
SPI-4 Ingress Port Buffer (32 x 128 byte FIFOs, 4K bytes, 16K segments)
...
128 bytes
Buffer 31
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| IDT88P8341BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8341BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8344 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
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