參數(shù)資料
型號(hào)： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 88/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
31 of 162
October 20, 2006
IDT IDT88K8483
WRB/SDI
I
CMOS
Pull-up
Schmitt Trigger
WRB is Microprocessor Write Control. Active low.
SDI is Serial Peripheral Interface (SPI) Chip Select. Active low.
RDB / SCLK
I
CMOS
Pull-up
Schmitt Trigger
RDB is Microprocessor Read Control. Active low.
SCLK is Serial Peripheral Interface (SPI) Clock.
CSB
I
CMOS
Pull-up
Schmitt Trigger
CSB is Microprocessor Chip Select. Active low.
INTB
O
CMOS
Open Drain
INTB is Microprocessor Interrupt. Active low.
SPIEN
I
CMOS
Pull-up
SPIEN is Serial Peripheral Interface (SPI) mode enable. Active high.
MPM
I
CMOS
Pull-up
MPM is Microprocessor mode Control. This signal controls the micro-
controller mode. 1 - Intel Mode. 0 - Motorola Mode.
JTAG Interface
TRSTB
I
CMOS
Pull-up
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and the JTAG TAP Controller. An external pull-up on the
board is recommended to meet the JTAG specification in cases where
the tester can access this signal.
TCK
I
CMOS
Pull-up
Schmitt Trigger
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller.
TMS
I
CMOS
Pull-up
JTAG Mode. The value on this signal controls the test mode select of
the boundary scan logic or JTAG Controller.
TDO
O
CMOS
tri-state
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller.
TDI
I
CMOS
Pull-up
JTAG Data Input. This is the serial data input to the boundary scan logic
or JTAG Controller.
Miscellaneous Interface
RESETB
I
CMOS
Pull-down
Hardware Reset. Active low.
TESTSE
I
CMOS
Pull-down
Test Scan Enable. Active high. Input used for IDT factory test. This sig-
nal should be pulled down for normal operation.
TIMEBASE
I/O
CMOS
Pull-up
Time Base. A positive edge on this signal updates the PMON counters.
Subsequent edges within approximately 4ms are be ignored.
GPIO[2:0]
I/O
CMOS
Pull-up
General Purpose I/O. These pins can be configured as general purpose
I/O pins.
Clock Interface
SPI4A_RCLK
SPI4B_RCLK
SPI4M_RCLK
ICMOS
Pull-up
Schmitt Trigger
Interface A/B/M Reference Clock.
DIV4
I
CMOS
Pull-up
Pre-scalar Select. Configuration pin.
Symbol1
I/O
Type2
Function
Comments
Table 2 Pin Description (Part 4 of 5)
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IDT88P8341BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8341BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
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