參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 40/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
134 of 162
October 20, 2006
IDT IDT88K8483
Packet Length Register
Burst Size Register
Random Control Register
BW
Bandwidth Level
00
MCLK
01
1/2 MCLK
10
1/4 MCLK
11
1/8 MCLK
Table 132 Bandwidth level as per field BW.
Field
Read/
Write
Bits
Length
Reset
State
Description
P_LEN
R/W
0:0 - 1:5
14
0xFF
This field determines the packet length to be generated using the
PRBS pattern. The actual packet length to be transmitted is
P_LEN + 1.
Table 133 Packet Length Register (Block Base=0x0B00, Register Offset=0x03)
Field
Read/Write
Bits
Length
Reset
State
Description
BURST_S
R/W
0:0 - 0:3
4
0xF
This field determines the burst size of the packets gener-
ated by the PSBR packet generator. The packets can be
transmitted in a random or a fixed burst as determined by
the BURST_RAND field in the Random Control Register
Table 134 Burst Size Register (Block Base=0x0B00, Register Offset=0x04)
Field
Read/Write
Bits
Length
Reset
State
Description
PLEN_RAND
R/W
0:0
1
0
This bit determines if the packet length of the packets gen-
erated by the PSBR packet generator is random or fixed.
0: Enable fixed packet length. It is fixed to P_LEN + 1.
P_LEN is defined in Packet Length Register (p. 134).
1: Enable random packet length. The packet length can be
from 1 to P_LEN + 1.
BURST_RAND
R/W
0:1
1
0
This bit determines if the burst size of the packets to be
transmitted is random or fixed.
0: Enable fixed burst size. It is fixed to (BURST_S+1)*16
bytes. BURST_S is defined in Burst Size Register
1: Enable random burst size. The burst size can vary from
16 bytes to (BURST_S+1)*16 bytes.
Table 135 Random Control Register (Block Base=0x0B00, Register Offset=0x05)
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