參數(shù)資料
型號: IDT88K8483BRI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 41/162頁
文件大?。?/td> 0K
描述: IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88K8483BRI
135 of 162
October 20, 2006
IDT IDT88K8483
LID Register
Synchronization Register
Bit Error Insertion Register
PMON Registers
Field
Read/
Write
Bits
Length
Reset
State
Description
LID
R/W
0:0 - 0:5
6
0
This field indicates the LID which is selected to transfer the
PRBS packet burst.
Table 136 LID Register (Block Base=0x0B00, Register Offset=0x06)
Field
Read/
Write
Bits
Length
Reset
State
Description
SYNCV
R/W
0:0
1
0
This field indicates the synchronization status of the PRBS detector.
0: Out of sync.
1: In sync.
SYNCI
R/W
0:1
1
0
This field captures any transaction in the field SYNCV.
0: No change.
1: Change in state from out of sync to in sync or vice-versa.
Write 1: Clear
Note: (1)The out of sync status can be due to any one of 3 reasons.
a) Resetting the device.
b) If field “DEN” in Enable Control Register (p. 133) is 0.
c) If excessive errors between regenerated sequence from the received data and received sequence.
(2) A transition from out of sync to in sync is caused by 48 consecutive error free bits.
(3) In the in sync state, each mismatched bit will generate a bit error event and will be forwarded to PMON.
Table 137 Synchronization Register (Block Base=0x0B00, Register Offset=0x07)
Field
Read/
Write
Bits
Length
Reset
State
Description
ERROR_INS
R/W
0:0
1
0
This field is used to insert a single bit error into the PRBS
generator.
0: Bit error is not inserted.
1: 1 bit error is inserted After the error is inserted, it auto clears.
Table 138 Bit Error Insertion Register (Block Base=0x0B00, Register Offset=0x08)
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