參數(shù)資料
型號: IDT88K8483BRI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 48/162頁
文件大小: 0K
描述: IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝: 24
系列: *
其它名稱: 88K8483BRI
141 of 162
October 20, 2006
IDT IDT88K8483
PMON Buffer M-T Overflow Indication Register
There are 2 registers.
PMON Buffer T-M Overflow Interrupt Control Register
There are 2 registers.
PMON Buffer M-T Overflow Interrupt Control Register
There are 2 registers.
Field
Read /
Write
Bits
Length Reset
State
Description
OVERFLOW[31:0]
R/W
0:0-3:7
32
0
This register indicates the overflow on a per LID basis from the main to tributary
SPI-4 interface. Bit 0 of register with offset 0x04 indicates overflow for LID 0, bit 3
for LID 3, bit 0 of 2nd register with offset 0x05 indicates overflow for LID 32 and so
on.
Read 1: Indicates overflow for that LID.
Read 0: Indicates no overflow for that LID.
Write 1: Clears the bit.
Table 142 PMON Buffer M-T Overflow Indication Register (Block Base=0x0F00, Register Offset=0x04-0x05)
Field
Read /
Write
Bits
Length Reset
State
Description
OVF_EN[31:0]
R/W
0:0-3:7
32
0
This register enables or disables the overflow indication for the LIDs which is
indicated in registers in Table 141.Bit 0 of register with offset 0x06 is for LID 0 and
bit 0 of register with offset 0x07 is for LID 32 and so on.
0: Disables overflow indication in PMON buffer T-M overflow indication register.
1: Enables overflow indication in PMON buffer T-M overflow indication register.
Table 143 PMON Buffer T-M Overflow Interrupt Control Register (Block Base=0x0F00, Register Offset=0x06-0x07)
Field
Read /
Write
Bits
Length Reset
State
Description
OVF_EN
R/W
0:0-3:7
32
0
This register enables or disables the overflow indication for the LIDs which is
indicated in registers in Table 142.Bit 0 of register with offset 0x08 is for LID 0 and
bit 0 of register with offset 0x09 is for LID 32 and so on.
0: Disables overflow indication in PMON buffer M-T overflow indication register.
1: Enables overflow indication in PMON buffer M-T overflow indication register.
Table 144 PMON Buffer M-T Overflow Interrupt Control Register (Block Base=0x0F00, Register Offset=0x08-0x09)
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