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參數(shù)資料
| 型號： | IDT88K8483BRI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 106/162頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI-4 EXCHANGE 3PORT 672-BGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88K8483BRI |
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October 20, 2006
IDT IDT88K8483
If the E_CSW_EN field is cleared to 0, then the DIP-2 is computed over all preceding status indications after last ‘11’ framing pattern. If
E_CSW_EN field is set to 1, and E_DIP_CSW field is set to 1, then the DIP-2 is computed over calendar selection word and all preceding status indi-
cations after last ‘11’ framing pattern. If E_CSW_EN field is set to 1, and E_DIP_CSW field is set to 0, then the DIP-2 is computed over all preceding
status indications after last ‘11’ framing pattern, excluding the calendar selection word.
In IN_SYNCH state, each DIP-2 error generates a DIP-2 error event towards to PMON. A single DIP-2 error sets all calendar LP’s status to ‘satis-
fied’. In IN_SYNCH state, the status is updated per cycle rather than updated all LP at the end of the frame. In OUT_OF_SYNCH state, the calendar’
LP’s status are fixed to ‘satisfied’. In the two-calendar modes, the MSB of calendar ID is extracted to CAL_ID field in SPI-4 Egress Calendar Switch
Control Register (p. 116). The CAL_ID field does not change in single calendar mode or in out of sync state.
The calendar length is configured in the E_CAL_LEN field in the SPI-4 Egress Calendar 0 Configuration Register (p. 114). In LVTTL mode, the
E_CAL_LEN field can be programmed with any value. In LVDS mode, the E_CAL_LEN field must be programmed with 4n-1 (n is an integer).
No status channel option
There is an option to configure the device to no status channel mode by the NO_STAT field in the SPI-4 Egress Configuration Register (p. 113). In
No status mode, the Egress synchronization is fixed at out of sync, there is no DIP-2 error check, and per LP status is fixed to ‘starving’.
Diagnose features
- Egress status channel clock detect. If there is no transition on MCLK clock in a 2048 MCLK hopping window, then the SLCK_AV field in the SPI-
4 Egress Status Register (p. 115) is cleared to 0. The SLCK_AV field transition from 1 to 0 generates an event forward to PMON. In LVDS I/O mode,
the device detects “no transition” on the LVDS input clock.
- DIP-4 error insertion. A number of consecutive (less than 16) DIP-4 errors can be generated. The number of error is configured by the
E_DIP_NUM field in the SPI-4 Egress Diagnostics Register (p. 115). When the E_ERR_INS field in the SPI-4 Egress Diagnostics Register (p. 115) is
set to 1, error insertion is triggered using the E_DIP_NUM field value.The E_ERR_INS field is self cleared when the correct number of errors is gener-
ated. The E_DIP_NUM field value is user-configured and is not changed internally.
- Force continuous training. The data channel generates continuous training pattern if E_FORCE_TRAIN field in the SPI-4 Egress Diagnostics
Register (p. 115) is set to 1.
- Egress port Buffer fill level. The egress Port Buffer fill level is indicated in the FILL_CUR field in the SPI-4 Egress Fill Level Register (p. 116). The
maximum port buffer fill level is configured by using the FILL_MAX field in the SPI-4 Egress Max Fill Level Register (p. 116).
Insert and Extract paths
OBC insert/extract path
A useful feature for diagnostics is the OBC (On Board Controller) insert and extract path.
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| IDT88P8341BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8341BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8344 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
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