參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 118/162頁
文件大小： 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
59 of 162
October 20, 2006
IDT IDT88K8483
Generic Interface
Overview
The auxiliary interface has two modes: QDR-II interface mode and generic interface mode. The auxiliary interface mode (QDR-II or generic) is
configured by the MEM field in the Auxiliary Interface Configuration Register (p. 129). The auxiliary interface has to be configured before the interface
is enabled. The auxiliary interface outputs (except for the clock) can be powered down by setting to 1 the AUX_PDN field in the Auxiliary Interface
Enable Register (p. 129). The interface is enabled by setting to 1 the AUX_EN field in the Auxiliary Interface Enable Register (p. 129).
The generic interface can be connected to an FPGA. The interface has 32 bits ingress data bus, 4 bits ingress control bus, 32 bits egress data bus
and 4 bits egress control bus. The 4 bits control bus carries the control information that indicates the transfer type, and the 32 bits data bus curries the
transfer data. The interface has also differential CLK ingress clock and differential CLK egress clock.
The ingress flow control messages are transmitted on the egress channel. The egress flow control messages are transmitted on the ingress
channel. The flow control mechanism provides both per link level flow control and interface level flow control.
The G_VREF signal should be connected to 0.75V generated from the VDDH15 power supply using regulator or pot-divider like MAX1510 as
Figure 28 IDT88K8483 and FPGA connections
Transfer Format for Normal Data
The generic interface format is defined to map 1-256 bytes payload in a proprietary transfer format. The transfer format for normal data is shown in
Figure 29 (DM is DUMMY information)
. The minimum payload transfer length is 2 words (1 word is 1 data cycle). The first word of a transfer
carries the LID information. LID[5:0] is mapped into B[5:0] of the first byte. The control field of the first transfer is SOP or SOT.
Figure 29 Generic Interface - Transfer Format for Normal Data
FPGA
G_EDAT[31:0]
G_ECTL[3:0]
G_IDAT[31:0]
EDAT[31:0]]
G_ECLKP
ECTL[3:0]
ICTL[3:0]
G_ICTL[3:0]
IDAT[31:0]
ECLKP
G_ECLKN
ECLKN
ICLKP
ICLKN
G_ICLKP
G_ICLKN
IDT88K8483
G_VREF
G_IMP
VDDH15/2
100 OHM
Ctrl[0]
DM
DAT[0]
LID
DM
B0/DM
B0
B3/Dummy B2/DM
B5/DM
D4/DM
B7/DM
B6/DM
Ctrl[1]
Ctrl[0]
Ctrl[1]
DAT[31]
CTL[0]
CTL[3]
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IDT88P8341BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8341BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
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