參數(shù)資料
型號(hào): IDT88K8483BRI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 39/162頁
文件大?。?/td> 0K
描述: IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88K8483BRI
133 of 162
October 20, 2006
IDT IDT88K8483
Auxiliary Initialization Control Register
PRGD Registers
Enable Control Register
Feedback Configuration Register
Bandwidth Control Register
Field
Read /
Write
Bits
Length Reset
State
Description
INIT_TRIG
R/W
0:0
1
0
Write 1 to initialize synchronization of the auxiliary interface.
AUTO_SYNCH
R/W
0:1
1
0:Test mode,
1:Embedded software controls initialization of the synchronization.
Table 128 Auxiliary Initialization Control Register
(Block Base=0x0A00, Register Offset=0x013)
Field
Read/
Write
Bits
Length
Reset
state
Description
GEN
R/W
0:0
1
0
This bit enables or disables the PRBS generator.
0: Disable PRBS generator.
1: Enable PRBS generator.
DEN
R/W
0:1
1
0
This bit enables or disables the PRBS detector.
0: Disable PRBS detector.The received PRBS is not detected and the payload
is discarded.
1: Enables PRBS detector to detect the received PRBS.
Table 129 Enable Control Register
(Block Base=0x0B00, Register Offset=0x00)
Field
Read/
Write
Bits
Length
Reset
State
Description
FBC
R/W
0:0 - 0:7
8
0
This field defines the feedback function for generating the PRBS
sequence.
FBC
R/W
1:0 - 1:7
8
0xC0
This field defines the feedback function for generating the PRBS
sequence.
FBC
R/W
2:0 - 2:7
8
0
This field defines the feedback function for generating the PRBS
sequence.
FBC
R/W
3:0 - 3:7
8
0
This field defines the feedback function for generating the PRBS
sequence.
Table 130 Feedback Configuration Register (Block Base=0x0B00, Register Offset=0x01)
Field
Read/
Write
Bits
Length
Reset
State
Description
BW
R/W
0:0 - 0:1
2
11
This field defines the bandwidth level for the PRBS generator and
checker as shown in Table 126.
Table 131 Bandwidth Control Register (Block Base=0x0B00, Register Offset=0x02)
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