參數資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數： 18/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
114 of 162
October 20, 2006
IDT IDT88K8483
SPI-4 Egress Calendar 0 Configuration Register
SPI-4 Egress Calendar 1 Configuration Register
Field
Read /
Write
Bits
Length Reset
State
Description
E_CAL_M
R/W
0:0-0:7
8
0x01
The E_CAL_M value programmed defines the number of times the calendar
sequence is repeated before a DIP-2 parity and “1 1” framing words are inserted1.
The actual CALENDAR_M value used is one more than the value programmed into
the E_CAL_M field.
E_CAL_LEN
R/W
1:0-1:6
7
0x07
This field specifies the egress calendar 0 length.
In LVTTL mode, the E_CAL_LEN can be programmed with any value.
In LVDS mode, it should be programmed with 4n-1, where n is an integer.Indicates
the length of the egress calendar 02. The actual calendar length CALENDAR_LEN3
is E_CAL_LEN+1.
Note:
1If the E_CSW_EN bit in SPI-4 Egress Calendar Switch Control Register (p. 116) is set to 1,then the E_CAL_M value defines the number of times the
calendar sequence is repeated before a DIP2 parity,’1 1’ framing word and calendar selection word are inserted.
2The calendar length CALENDAR_M must be at least as large as the number of active SPI-4 egress LPs. CALENDAR_M must match the number of entries in the
3CALENDAR_LEN and CALENDAR_M are described in the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1).
Table 77
SPI-4 Egress Calendar 0 Configuration Register (Block Base=0x0800, Register Offset=0x03)
Field
Read /
Write
Bits
Length Reset
State
Description
E_CAL_M
R/W
0:0-0:7
8
0x01
The E_CAL_M value programmed defines the number of times the calendar
sequence is repeated before a DIP-2 parity and “1 1” framing words are inserted1.
The actual CALENDAR_M value used is one more than the value programmed into
the E_CAL_M field.
E_CAL_LEN
R/W
1:0-1:6
7
0x07
This field specifies the egress calendar 1 length.
In LVTTL mode, the E_CAL_LEN can be programmed with any value.
In LVDS mode, it should be programmed with 4n-1, where n is an integer. Indicates
the length of the egress calendar 12. The actual calendar length CALENDAR_LEN3
is E_CAL_LEN+1.
Note:
1If the E_CSW_EN bit in SPI-4 Egress Calendar Switch Control Register (p. 116) is set to 1,then the E_CAL_M value defines the number of times the
calendar sequence is repeated before a DIP2 parity,’1 1’ framing word and calendar selection word are inserted.
2The calendar length CALENDAR_M must be at least as large as the number of active SPI-4 ingress LPs. CALENDAR_M must match the number of entries in
3CALENDAR_LEN and CALENDAR_M are described in the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1).
Table 78
SPI-4 Egress Calendar 1 Configuration Register (Block Base=0x0800, Register Offset=0x04)
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