參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 87/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
30 of 162
October 20, 2006
IDT IDT88K8483
QDR_D[35:0]/
G_ECTL[3:0],
G_EDAT[31:0]
O
HSTL
QDR_D[35:0] is QDR-II Output Data Bus. This bus is used to transfer
the data to the QDR-II / FPGA devices. It is driven out on the rising
edge of K and K clocks during write operation.
G_ECTL[3:0] is Generic Interface Egress Control Bus.
G_EDAT[31:0] is Generic Interface Egress Data Bus.
QDR_Q[35:0]/
G_ICTL[3:0],
G_IDAT[31:0]
I
HSTL
QDR_Q[35:0] is QDR-II Input Data Bus. This bus is used to transfer
data from the QDR-II / FPGA devices. It is sampled on the rising edge
of K and K clocks during read operation.
G_ICTL[3:0] is Generic Interface Ingress Control Bus.
G_IDAT[31:0] is Generic Interface Ingress Data Bus.
QDR_RB
O
HSTL
QDR_RB is QDR-II Read Control. This active low signal is driven out on
the rising edge of K clock. When it active, a read operation is initiated.
When it deasserted, the read port is deselected.
QDR_WB
O
HSTL
QDR_WB is QDR-II Write Control. This active low signal is driven out
on the rising edge of K clock. When it asserted, a write operation is initi-
ated. When it deasserted, the write port is deselected.
QDR_K / G_ECLKP
O
HSTL
QDR_K is QDR-II Positive Output Clock. The rising edge of QDR_K is
used to capture input data to the device and to drive out data from the
device.
G_ECLKP is Generic Interface Positive Egress Clock.
QDR_KB / G_ECLKN
O
HSTL
QDR_KB is QDR-II Negative Output Clock. The rising edge of QDR_KB
is used to capture input data to the device and to drive out data from the
device.
G_ECLKN is negative Generic Interface Egress Clock.
QDR_CQ / G_ICLKP
I
HSTL
QDR_CQ is QDR-II Synchronous Positive Input Clock. The rising edge
of QDR_CQ is tightly matched to the data inputs and can be used as a
data valid indication.
G_ICLKP is Generic Interface Positive Ingress Clock.
QDR_CQB / G_ICLKN
I
HSTL
QDR_CQB is QDR-II Synchronous Negative Input Clock. The rising
edge of QDR_CQB is tightly matched to the data inputs and can be
used as a data valid indication.
G_ICLKN is Generic Interface Negative Ingress Clock.
QDR_VREF / G_VREF
I
Analog
Reference
QDR_VREF is 0.75 Reference Voltage Input. This static input is used to
set reference level for HSTL inputs and outputs as well as AC measure-
ment points. This pin should be connected to VDDH15/2.
G_VREF is 0.75 Reference Voltage Input. This pin should be con-
nected to VDDH15/2.
QDR_IMP / G_IMP
I
Reference
QDR_IMP is Reference Input. This signal must be connected via an
external pull-down 100 OHM resistor to VSS.
G_IMP is Reference Input. This signal must be connected via an exter-
nal pull-down 100 OHM resistor to VSS.
Microprocessor Interface
ADR[5:0]
I
CMOS
ADR[5:0] is Microprocessor Address Bus. This bus is used to transfer
the address from the micro-controller.
DAT[7:0] / SDO
I/O
CMOS
DAT[7:0] is Microprocessor Data Bus. This bus is used to transfer the
data between the device and the microprocessor.
SDO (DAT[0]) is Serial Peripheral Interface (SPI) data.
Symbol1
I/O
Type2
Function
Comments
Table 2 Pin Description (Part 3 of 5)
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IDT88P8341BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8341BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
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