參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 17/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
113 of 162
October 20, 2006
IDT IDT88K8483
SPI-4 Egress Configuration Register
SPI-4 Egress Training Parameter Register
Field
Read /
Write
Bits
Length Reset
State
Description
E_INSYNC_THR
R/W
0:0-0:4
5
0x1F
The number of consecutive error free DIP 2 required to make the egress status
channel state machine transition from out of sync to in sync.The actual number of
error free DIP 2 that need to be detected is E_OUTSYNC_THR+1.
E_CLK_EDGE
R/W
0:5
1
0
This field controls the edge of the status clock in LVTTL mode, at which the status
information will be sampled.
0:Sampling is done at rising edge.
1:Sampling is done at falling edge.
E_LOW
R/W
0:6
1
For optimum device performance, this bit should be set to ‘0’ or ‘1’ depending on the
SPI-4 egress data clock frequency.
0: EDCLK is higher than or equal to 200 MHz.
1: EDCLK is lower than 200 MHz.
NOSTAT
R/W
0:7
1
0
The NOSTAT bit enables the no status channel option. Once NOSTAT is set, the
status channel is ignored. There is no DIP-2 error checking, and no status channel
updating. The received status is fixed to starving. The data channel is put into the in
sync state.
0:Normal status channel operation.
1:No status channel option is selected.
E_OUTSYNC_THR
R/W
1:0-1:3
4
0xF
The number of consecutive DIP 2 errors needed for the egress state to transition
from in sync to out of sync.The actual number of DIP 2 errors that need to be
detected is E_INSYNC_THR+1.
Note: Please refer to SPI-4 Ingress State Machine (p. 44) for an illustration of out of sync and in sync state.
Table 75
SPI-4 Egress Configuration Register (Block Base=0x0800, Register Offset=0x01)
Field
Read /
Write
Bits
Length Reset
State
Description
DATA_MAX_T
R/W
0:0-2:7
24
0
The SPI-4 egress DATA_MAX_T field is the maximum time interval between
scheduling of training sequences on the egress data path interface. The unit is in 28
SPI-4 data cycles.
ALPHA
R/W
3:0-3:7
8
0
The SPI-4 egress ALPHA field is the number of repetitions of the data training
sequence that must be scheduled every DATA_MAX_T cycles. The value for alpha
used is actually one more than the ALPHA value programmed into the ALPHA field.
Note: The purpose of the data path training sequence is for the deskew of bit arrival times on the data and control lines.
Table 76
SPI-4 Egress Training Parameter Register (Block Base=0x0800, Register Offset=0x02)
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