參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 160/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
97 of 162
October 20, 2006
IDT IDT88K8483
PFP T-M insert data register for module A
PFP T-M extract control register for module A
PFP T-M extract data register for module A
PFP M-T insert control register for module A
PFP M-T insert data register for module A
Field
Read/
Write
Bits
Length
Reset
State
Description
DATA
W
0:0-0:7
8
0
This field holds the data to be written into the insert FIFO.
Table 37 PFP T-M insert data register(Register Offset=0x1)
Field
Read/
Write
Bits
Length
Reset
State
Description
DATA_AVAILABLE
R/W
0:0
1
0
This bit indicates the availability of data in the extract FIFO. If data is avail-
able, then it is extracted from the FIFO.
Read 0: Data is not available in the FIFO.
Read 1: Data is available in the FIFO.
Write 0: Clears the extract FIFO.
Note: After data is extracted from the FIFO, a transfer extract event will be forwarded to the interrupt module.
Table 38 PFP T-M extract control register (Register Offset=0x2)
Field
Read/
Write
Bits
Length
Reset
State
Description
DATA
R
0:0-0:7
8
0
This field holds the content read from the FIFO.
Table 39 PFP T-M extract data register (Register Offset=0x3)
Field
Read/
Write
Bits
Length
Reset
State
Description
DATA_AVAILABLE
R/W
0:0
1
0
This field indicates the availability of insert FIFO for M-T insertion.
Read 0: FIFO is available
Read 1: FIFO not available
Write 1: Launch data after writing transfer and overhead into the FIFO.
Note: The DATA_AVAILABLE flag will self clear if FIFO is emptied by PFP. This event will be forwarded to interrupt module.
Table 40 PFP M-T insert control register (Register Offset=0x4)
Field
Read/
Write
Bits
Length
Reset
State
Description
DATA
W
0:0-0:7
8
0
The content to be inserted into the insert FIFO is written into this field.
Table 41 PFP M-T insert data register (Register Offset=0x5)
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