參數(shù)資料
型號(hào)： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 114/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
55 of 162
October 20, 2006
IDT IDT88K8483
QDR-II Interface
Overview
The auxiliary interface has two modes: QDR-II interface mode and generic interface mode. The auxiliary interface mode (QDR-II or generic) is
configured by the MEM field in the Auxiliary Interface Configuration Register (p. 129). The auxiliary interface has to be configured before the interface
is enabled. The auxiliary interface outputs (except for the clock) can be powered down by setting to 1 the AUX_PDN field in the Auxiliary Interface
Enable Register (p. 129). The interface is enabled by setting to 1 the AUX_EN field in the Auxiliary Interface Enable Register (p. 129).
The QDR-II interface can be connected to 18M bit QDR-II burst of two SRAM with 36 bit data at 200 MHz. The interface has 36 bits input data bus,
36 bits output data bus (four bytes) and 18 bits address bus. The 36 bits data bud include 32 bits payload data and 4 bits overhead. The interface has
also QDR_K and QDR_KB output clocks and QDR_CQ and QDR_CQB input clocks. The device supports up to 64 independent FIFOs in the memory,
and a full duplex 10Gbps data-stream to and from the memory. It also supports flow control per LID.
The QDR_VREF signal should be connected to 0.75V generated from the VDDH15 power supply using regulator or potential divider such as the
Figure 23 IDT88K8483 and IDT7172604 QDR-II SRAM connections
QDR-II Transfer format
In a single write burst a transfer with 1 to 256 bytes is stored in the memory. A format is defined to map the 1 to 256 bytes in a proprietary transfer
format. The format adds 4 overhead bits to each 32 payload bits group. The transfer format overhead includes the total length of the payload (in units
of bytes), packet delineation and error tags. The first two overhead fields of a transfer format contain the higher bit of the transfer length, and the
transfer beginning field. The third overhead field contains packet delineation and error tag. The fourth overhead field contains the last two bits of the
transfer length. All the remaining overhead fields are fixed to 0’b0000.
The minimum length of the transfer format is 4 words (36 bit). The payload is padded with a fixed 0xFF pattern. The transfer length is equal to an
integer multiple of 2 words (36 bit).
Memory segmentation
The external SRAM is segmented in a configurable number of FIFOs with equal size. The number of the FIFOs is configured by EBC field in the
Auxiliary Interface Configuration Register (p. 129). The memory is managed based on memory segment size of 256byte.
IDT88K8483
IDT7172604
QDR_A[17:0]
QDR_D[35:0]
QDR_Q[35:0]
D[35:0]
Q[35:0]
SA[35:0]
R
QDR_RB
QDR_WR
QDR_K
QDR_KB
K
W
QDR_CQ
QDR_VREF
QDR_IMP
QDRII SRAM
18Mb burst of 2
QDR_CQB
CQ
VDDH15/2
100 OHM
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