參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 135/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
74 of 162
October 20, 2006
IDT IDT88K8483
Ensure that the buffer has sufficient drive capability to supply all loads. When using a buffer to drive any of the JTAG TAP pins, it may be necessary to
include an external resistor to ensure the pin is set to the correct state when the buffer is idle. Thus, TRSTB should have an external resistor to ground
when driven by an external buffer and TMS and TCK should each have an external pull-up.
The JTAG instructions are described in Table 11. The JTAG ID information is described in Table 12.
GPIO
The device has 3 general purpose input/output pins. The pins’ direction is independently controlled by the DIR_OUT field in the GPIO Direction
Register (p. 145). The logical level on the pins is controlled by the LEVEL field in the GPIO Level Register (p. 146). The LEVEL field reflects the status
of any bit which is selected from the indirect access space if enabled. A bit in the indirect access space can be selected by the ADDRESS and BIT
fields in the GPIO Link Table (p. 146). A bit can be enabled by the REFLECT_EN field in the GPIO Link Table (p. 146). IDT recommends to connect all
the unused GPIO signals to an FPGA or microprocessor pins for debugging purpose.
Power Supply
The IDT88K8483 Power Supplies can be generated as shown in the design example in Figure 41 IDT88K8483 Power Supply Genera-
The IDT88K8483 system should have the following:
1. Connect the VDDA25 signals through filter to The VDDH25 / VDDL25 signals as described in Figure 42 IDT88K8483 VDDA25 Filter Circuit
2. Connected together the VDDH25 signals and the VDDL25 signals.
3. Separate the VDDC12 signals and VDDL12 signals.
4. Generate the VDDL25 / VDDH25 signals from VDDT33 signals.
5. Generate the V TT075 signals from VDDH15 signals.
Instructions
Instruction Codes
Function Description
EXTEST
000
Test the function to other devices
IDCODE
001
Used to connect the identification register
HIGHZ
100
Set outputs to Hi-Z state
CLAMP
011
Clamp the output latches
SAMPLE
010
Sample all the inputs and outputs
RUNBIST
110
BIST
USERCODE
101
User code
BYPASS
111
Used to bypass the device
Table 11 JTAG Instruction Code
Version
Part Number
Manufacture ID
Fixed
0
0x4af
0x33
1
Table 12 JTAG ID
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相關代理商/技術參數(shù)
參數(shù)描述
IDT88P8341BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8341BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
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