參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 85/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
29 of 162
October 20, 2006
IDT IDT88K8483
SPI4A_ID[15:0]_P
SPI4B_ID[15:0]_P
SPI4M_ID[15:0]_P
SPI4A_ID[15:0]_N
SPI4B_ID[15:0]_N
SPI4M_ID[15:0]_N
I
LVDS
Ingress Data Bus. This data bus is used to carry ingress payload data
and in-band control words.
RDAT[15:0]
TDAT[15:0]
SPI4A_IDCLK_P
SPI4B_IDCLK_P
SPI4M_IDCLK_P
SPI4A_IDCLK_N
SPI4B_IDCLK_N
SPI4M_IDCLK_N
I
LVDS
Ingress Data Clock. This clock is associated with the ingress data bus
(ID) and the control signal (ICTL).
RDCLK
TDCLK
SPI4A_ICTL_P
SPI4B_ICTL_P
SPI4M_ICTL_P
SPI4A_ICTL_N
SPI4B_ICTL_N
SPI4M_ICTL_N
I
LVDS
Ingress Control. This signal is high when a control word is present on
the ingress data bus (ID) and it is low otherwise.
RCTL
TCTL
SPI4A_ISTA[1:0]_P
SPI4B_ISTA[1:0]_P
SPI4M_ISTA[1:0]_P
SPI4A_ISTA[1:0]_N
SPI4B_ISTA[1:0]_N
SPI4M_ISTA[1:0]_N
O
LVDS
Ingress FIFO Status LVDS. These signals are used to carry ingress
round-robin FIFO status information, along with associated error detec-
tion and framing.
RSTAT[1:0]
TSTAT[1:0]
SPI4A_ISCLK_P
SPI4B_ISCLK_P
SPI4M_ISCLK_P
SPI4A_ISCLK_N
SPI4B_ISCLK_N
SPI4M_ISCLK_N
O
LVDS
Ingress Status Clock LVDS. This clock is associated with the ingress
FIFO status signals (ISTA).
RSCLK
TSCLK
SPI4A_ISTA_T[1:0]
SPI4B_ISTA_T[1:0]
SPI4M_ISTA_T[1:0]
OLVTTL
Pull-up
Ingress FIFO Status LVTTL. These signals are used to carry ingress
round-robin FIFO status information, along with associated error detec-
tion and framing.
RSTAT[1:0]
TSTAT[1:0]
SPI4A_ISCLK_T
SPI4B_ISCLK_T
SPI4M_ISCLK_T
OLVTTL
Pull-up
Schmitt Trigger
Ingress Status Clock LVTTL. This clock is associated with the ingress
FIFO status signals (ISTA_T).
RSCLK
TSCLK
SPI4A_BIAS
SPI4B_BIAS
SPI4M_BIAS
Analog
BIAS. This signal must be connected via an external pull-down 1% 3K
Ω
resistor to VSS.
SPI4A_VREF
SPI4B_VREF
SPI4M_VREF
Analog
REF. These signals are reference for LVDS. These signals should be
connected to VDDL12.
SPI4A_LVDSSTA
SPI4B_LVDSSTA
SPI4M_LVDSSTA
ICMOS
Pull-down
Status Channel Control. This signal controls the status signal I/O type.
A hardware reset or software reset must be perform after changing the
level of this signal. 1 - LVDS status. 0 - LVTTL status.
QDR-II Interface / Generic Interface (Auxiliary Interface)
QDR_A[17:0]
O
HSTL
QDR_A[17:0] is QDR-II Address Bus. This bus is used to transfer the
address to the QDR-II / FPGA devices. It is driven out on the rising
edge of K and K clocks during write or read operation.
Symbol1
I/O
Type2
Function
Comments
Table 2 Pin Description (Part 2 of 5)
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IDT88P8341BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8341BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
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