參數資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數： 132/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
71 of 162
October 20, 2006
IDT IDT88K8483
Design Consideration
System Reset
There are two methods for resetting the IDT88K8483: hardware reset and software reset. During reset the output clocks are not toggled.
Hardware Reset
The RESETB input requires an active low pulse to reset the internal logic.
Software Reset
The software reset is triggered by setting to 1 the RST field in Global Software Reset Register (p. 90). The response to a software reset is identical
to a hardware rest except that software reset does not change the N field in the MCLK Divider Sticky Register (p. 104), so it does not impact the clock
generators. After software reset the microprocessor should have delay of at least 2ms before accessing the device.
Power On Sequence
Figure 38 Power-on-Reset Sequence
A correct power-on-reset sequence is crucial for the normal behavior of the device. The power-on-reset sequence includes the following signals:
RCLK (SPI4A_RCLK, SPI4B_RCLK, SPI4M_RCLK), VDD (VDD33, VDDL25, VDDH25, VDDH15, VDDL12, VDDC12, VTT) and RESETB (RESETB).
illustrates the recommended implementation for the power-on-reset sequence for the device. IDT
recommends powering up the 3.3V (VDD33) power supply first, the 2.5V (VDDL25, VDDH25) power supply second, the 1.5V (VDDH15) power supply
third, the 1.2V (VDDC12, VDDL12) power supply fourth, and the 0.75V (VTT) power supply last. The power supplies can be also powered up in the
same time. There is no requirement for the minimum or maximum delay between the power-up of the power supplies. The power supplies should be
powered off in the reverse order. The power ramp should not be faster than 100us.
When the power supplies are powered up, the RESETB signal should be at low level. During power-on-reset, after the VDD, RCLK and the config-
uration signals are stable, the RESETB signal should remain at a low level at least 10ms (symbol “T1”) to reset the internal logic. After the RESETB
pulse ends, the device starts generating the SPI-4 external output clocks and the MCLK internal clock.
T1
RCLK
VDD33
RESETB
T3
T2
VDDC12
.
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IDT88P8341BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8341BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
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