參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 134/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
73 of 162
October 20, 2006
IDT IDT88K8483
The internal JTAG logic of each device powers up in an unknown state, so it is necessary at power-on to reset it to the Test-Logic-Reset state so
that the chip operates properly. This can be done in one of the three different ways:
1. TRSTB is pulled low by a resistor. TRSTB must also connect to the JTAG connector, and the JTAG tester must drive TRSTB high for JTAG
testing.
2. A low pulse is applied to TRSTB at power on as shown in Figure 40 TRSTB Signal During Power-On Reset p.73. Note that a falling
edge is not required on TRSTB. TRSTB can then be held high as long as TMS is also pulled high, thereby keeping the logic in the reset state.
This method is appropriate if the JTAG tester does not drive TRSTB.
3. TCK can be clocked five or more times while TMS is held high. In this case, TRSTB can be pulled high. This method is also appropriate if the
JTAG tester does not have TRSTB.
Figure 39 JTAG Daisy Chain
The TRSTB signal is an option reset pin and may not be available on all JTAG test connectors. TRSTB should be held high during JTAG testing.
Once in the Test-Logic-Reset test, the JTAG logic will remain in this state as long as TMS is high, regardless of the state of TRSTB.
Figure 40 TRSTB Signal During Power-On Reset
The TCK signal should be carefully routed on board according to standard layout design to minimize skew and noise problems.
JTAG specifications require that pull-up resistors be supplied internally to the TDI, TRSTB, and TMS pins in the chips. Very long JTAG chains or
parts from different vendors may present significant loading to the controller. To compensate for this, the designer should include buffers on TMS,
TRSTB and TCK to account for unknown device impedance. For systems with several components, the designer should use a high fan-out buffer.
TDI
JTAG Connector
TCK
TMS
TRSTB
TDO
TDI
IDT88K8483 - 1
TCK
TMS
TRSTB
JTDO
TDI
IDT88K8483 - 2
TCK
TMS
TRSTB
TDO
TCK
TMS
TRSTB
TCK
TMS
TRSTB
VDD
TCK
TMS
TRSTB
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參數(shù)描述
IDT88P8341BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8341BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
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