參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 47/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
140 of 162
October 20, 2006
IDT IDT88K8483
PMON Buffer T-M Overflow Indication Register
There are 2 registers.
T_DIP4_EN
R/W
1:7
1
0
Tributary SPI4 DIP-4.
0: Disables the interrupt.
1: Enables the interrupt.
T_BUSERR_EN
R/W
2:0
1
0
Tributary SPI4 bus error.
0: Disables the interrupt.
1: Enables the interrupt.
T_ISYNC_EN
R/W
2:1
1
0
Tributary ingress synch status change.
0: Disables the interrupt.
1: Enables the interrupt.
T_ESYNC_EN
R/W
2:2
1
0
Tributary Egress synch status change.
0: Disables the interrupt.
1: Enables the interrupt.
M_DIP2_EN
R/W
2:3
1
0
Main SPI4 DIP-2.
0: Disables the interrupt.
1: Enables the interrupt.
M_DIP4_EN
R/W
2:4
1
0
Main SPI4 DIP-4.
0: Disables the interrupt.
1: Enables the interrupt.
M_BUSERR_EN
R/W
2:5
1
0
Main SPI4 bus error.
0: Disables the interrupt.
1: Enables the interrupt.
M_ISYNC_EN
R/W
2:6
1
0
Main ingress synch status change.
0: Disables the interrupt.
1: Enables the interrupt.
M_ESYNC_EN
R/W
2:7
1
0
Main Egress synch status change.
0: Disables the interrupt.
1: Enables the interrupt.
Note: Writing a 1 to any field in this register, causes an interrupt to be generated based on the occurrence of that particular event indicated in the corresponding
field in Table 139. The interrupt appears as an active low on the INTB pin in the microprocessor interface.
Field
Read /
Write
Bits
Length Reset
State
Description
OVFERFLOW[31:0]
R/W
0:0-3:7
32
0
This register indicates the overflow on a per LID basis from the tributary to main
SPI-4 interface. Bit 0 of register with offset 0x02 indicates overflow for LID 0, bit 3
for LID 3, bit 0 of 2nd register with offset 0x03 indicates overflow for LID 32 and so
on.
Read 1: Indicates overflow for that LID.
Read 0: Indicates no overflow for that LID.
Write 1: Clears the bit.
Table 141 PMON Buffer T-M Overflow Indication Register (Block Base=0x0F00, Register Offset=0x02-0x03)
Field
Read /
Write
Bits
Length Reset
State
Description
Table 140 PMON Event Interrupt Enable Register (Block Base=0x0F00, Register Offset=0x01)
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