
IBM2520L8767
IBM Processor for ATM Resources
atmrm.toc.01
08/27/99
Table of Contents
Page vii
Transmit Enqueue Primitive ........................................................................................................... 224
Resume Transmission Primitive ..................................................................................................... 224
Close Connection Primitive ............................................................................................................ 225
Start/Stop Timer Primitive ............................................................................................................... 225
Timeslot Prescaler Register ........................................................................................................... 226
Current Timeslot Counter ............................................................................................................... 226
Timing Data Base Address ............................................................................................................. 227
CSKED Control Register ................................................................................................................ 227
Transmit Segmentation Throttle Register .......................................................................................229
Transmit Segmentation Throttle Counter .......................................................................................230
MPEG Conversion Register ........................................................................................................... 230
GFC Reset Values .......................................................................................................................... 231
ABR Timer Prescaler Register ....................................................................................................... 232
RM Cell Timer ................................................................................................................................. 232
Performance Registers ....................................................................................................................... 233
High Priority Bandwidth Limit Register ........................................................................................... 233
Medium Priority Bandwidth Limit Register ...................................................................................... 234
Low Priority Bandwidth Limit Register ............................................................................................234
High Priority Cells Transmitted Counter ......................................................................................... 235
Medium Priority Cells Transmitted Counter .................................................................................... 235
Low Priority Cells Transmitted Counter .......................................................................................... 236
Debugging Register Access .............................................................................................................. 237
High Priority Serviced Counter ....................................................................................................... 237
Medium Priority Serviced Counter .................................................................................................. 237
Low Priority Serviced Counter ........................................................................................................ 238
Slow Serviced Counters .................................................................................................................238
Timer Serviced Counters ................................................................................................................ 239
CSKED Status Register .................................................................................................................. 240
CSKED Interrupt Enable Register .................................................................................................. 241
Timing Data Array ........................................................................................................................... 241
State Machine Variables .................................................................................................................242
ATM Transmit Buffer Segmentation (SEGBF) .................................................................................. 243
SEGBF Block Diagram ........................................................................................................................243
SEGBF Software LCD Enqueue ..................................................................................................... 245
SEGBF Force HEC Value .............................................................................................................. 246
SEGBF Control Register ................................................................................................................ 247
SEGBF Status Register .................................................................................................................. 249
SEGBF Invalid LCD Register ......................................................................................................... 250
SEGBF Software LCD Complete .................................................................................................... 251
SEGBF Interrupt Enable Register .................................................................................................. 251
SEGBF Total User Cells Transmitted ............................................................................................. 252
SEGBF Total User Cells Transmitted with CLP=0 .........................................................................252
SEGBF Total NUD Cells Transmitted ............................................................................................. 253
SEGBF Cell Queue Status ............................................................................................................. 254
SEGBF Last Active LCD Data Registers ........................................................................................ 255
SEGBF PID High and Low Limit Register ...................................................................................... 256
SEGBF Last Active LCD Address 0 ............................................................................................... 257
SEGBF Last Active LCD Address 1 ............................................................................................... 258
MPEG-2 PCR Increment Register .................................................................................................. 259
MPEG-2 Local PCR High ............................................................................................................... 260
MPEG-2 Local PCR Low ................................................................................................................ 261