
IBM2520L8767
IBM Processor for ATM Resources
atmrm.chapt05.01
08/27/99
Processor Core (PCORE)
Page 357 of 553
Interrupt Controller
This logic manages the interrupts that are passed on to the 401 core. There are two levels of interrupt for the
core, Critical Interrupts and Normal Interrupts. Interrupts can be taken from both on-chip and off-chip sources.
PCORE has a variety of interrupt source and enable registers.
Clock & Power Management
This logic controls the various sleep and wakeup options for the 401 core.
Processor Local Bus(PLB)
The PLB is used as an interface between the 401 core and its variety of slave devices. The 401 core Instruc-
tion bus and the 401 core Data bus are each connected as masters to this bus. The Instruction bus is
connected as Master 0. The Data bus is connected as Master 1.
Bridge
The bridge translates processor space addresses to slave subsystem addresses. When a PLB read or write
transaction is issued from the PLB, the bridge function translates the address from the processor address to
the slave subsystem address and starts a slave system access.
SRAM
There is an on-chip SRAM for the use of the processor. This SRAM is typically used only by the processor,
therefore, it has a generally predictable access time. This SRAM would typically be mapped into the proces-
sor’s address space. There are a number of different ways that this can be done.
Control Memory
Control Memory can be accessed by the processor. This memory may be mapped into the processor space
in a number of different ways.
Packet Memory
Packet Memory can be accessed by the processor. This memory may be mapped into the processor space in
a number of different ways. Packet memory space also includes the virtual memory space of the
IBM2520L8767.
PCI Master Interface-External
The processor can access the PCI bus through this interface. Parts of PCI space are mapped into processor
space. There are a number of different ways that this can be mapped into processor space.
IBM2520L8767 Register Space
This access mode of the PCI Master Interface allows access to the internal IBM2520L8767 registers. This
access is handled internally and does not affect the external PCI bus.