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參數(shù)資料
| 型號(hào)： | IBM2520L8767 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Asynchronous Transfer Mode Processor for ATM Resources(IBM異步轉(zhuǎn)換模式 ATM資源管理微處理器) |
| 中文描述： | IBM的異步傳輸模式ATM的處理器資源（IBM的異步轉(zhuǎn)換模式自動(dòng)柜員機(jī)資源管理微處理器） |
| 文件頁(yè)數(shù)： | 180/573頁(yè) |
| 文件大?。?/td> | 7235K |
| 代理商： | IBM2520L8767 |
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IBM2520L8767
IBM Processor for ATM Resources
ATM Virtual Memory Logic (VIMEM)
Page 160 of 553
atmrm.chapt04.01
08/27/99
6.9: VIMEM Access Status Register
This register contains information regarding the current status of the virtual memory logic mainly with respect
to detected error access conditions. See
Note on Set/Clear/Read Type Registers
on page 71 for more details
on addressing.
Length
32 bits
Type
Read/Write
Address
XXXX 0D60 and 64
Power On Value
X’0000’
Restrictions
None
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Description
31-17
Reserved.
16
When set, this bit indicates that the required conditions for the control, packet, and virtual base registers has not been satis-
fied. The required conditions are: control base
<
packet base
<
virtual base
15
When set, this bit indicates that the virtual memory logic has detected a page fault error when attempting to read memory.
This indicates that no real buffer was available to map into the virtual address space when required. All virtual reads that fail
during a page fault regardless of the requesting entity will cause this bit to be set. If the corresponding bit is reset in the lock
register, the read operation will complete, but with invalid data.
14
When set, this bit indicates that a control memory access was detected that was above the value contained in the Packet
memory offset register for single bank configurations, or in a multiple bank configuration that the high address bits 31 - 27
were not zero.
13
When set, this bit indicates that a packet memory access of address zero was detected in single bank mode, or that a packet
address was detected that contained an address out of range (high five bits non-zero).
12
When set, this bit indicates that the virtual memory logic has detected a virtual memory operation that attempted to access a
map that was not marked as valid. A virtual buffer map is marked valid by the POOLS entity when the buffer is originally
acquired, and is marked as invalid when the buffer is freed back to POOLS. Receiving this error indication, typically means
that the software is trying to use a buffer that has not been acquired through the normal means, or trying to use a buffer that
has already be freed, or that memory has been corrupted. The valid indication that is checked by the hardware is the value
X’656’ in the first 16 bits of the eight-byte map entry being accessed. To determine the failing address, the memory control
entity can be locked on this type of failure, and the information saved by the memory controller, along with the base registers
in this entity can be used to determine which map was being accessed at the time of failure.
11
When set, this bit indicates that the virtual memory logic has detected a non-recoverable page fault error when attempting to
write memory. This indicates that no real buffer was available to map into the virtual address space when required. All virtual
writes that fail during a page fault with the exception of BCACH and RAALL operations will cause this bit to be set.
10
When set, this bit indicates that the virtual memory logic has detected a recoverable page fault error when attempting to write
memory. This indicates that no real buffer was available to map into the virtual address space when required. Operations
from BCACH and RAALL will cause this bit to be set instead of the non-recoverable bit because the software can recover
from these failures. If a BCACH write to virtual memory fails in this manner, the packet header of the frame being updated
will be updated to indicate the failure. Software can check the field in the packet header to ensure that the DMA operation
completed successfully. If such a packet is enqueued to CSKED, the packet header is checked and will prevent the frame
from being passed on to the segmentation logic. The frame will generate a BAD transmit event in RXQUE instead. If a failure
is indicated, the software must perform any required recovery actions. If a RAALL write to virtual memory fails in this manner,
the packet currently being received is dropped, it is up to the software to perform any recovery operations that are required.
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