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| 型號(hào)： | ARM7TDMI-S |
| 英文描述： | ARM7TDMI-S Microprocessor Core preliminary technical manual 5/00 |
| 中文描述： | 的ARM7TDMI - S微處理器核的初步技術(shù)手冊(cè)5 / 00 |
| 文件頁(yè)數(shù)： | 73/184頁(yè) |
| 文件大?。?/td> | 1147K |
| 代理商： | ARM7TDMI-S |
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Bus Cycle Types
Rev. A
4-3
Copyright 2000 by LSI Logic Corporation. All rights reserved.
an internal cycle (I), during which the ARM7TDMI-S core does not
require a transfer because it is performing an internal function, and
no useful prefetching can be performed at the same time
a coprocessor register transfer cycle (C), during which the
ARM7TDMI-S core uses the data bus to communicate with a
coprocessor, but does not require any action by the memory system.
these cycles are described in more detail in the following subsections.
4.2.1 Nonsequential Cycles (N)
A nonsequential cycle is the simplest form of an ARM7TDMI-S bus cycle.
It occurs when the ARM7TDMI-S core requests a transfer to or from an
address that is unrelated to the address used in the preceding cycle. The
memory controller must initiate a memory access to satisfy this request.
The address class signals (ADDR, WRITE, SIZE, PROT, LOCK) and
TRANS[1:0] = N cycle are driven on the bus. At the end of the next bus
cycle, the data is transferred between the CPU and the memory, as
illustrated in
Figure 4.2
.
Figure 4.2
Nonsequential Memory Cycle
The ARM7TDMI-S core can perform back-to-back, nonsequential
memory cycles. These cycles happen, for example, when an STR
instruction is executed, as shown in
Figure 4.2
. If you are designing a
memory controller for the ARM7TDMI-S core, and your memory system
cannot cope with this case, use the CLKEN signal to extend the bus
cycle to allow sufficient cycles for the memory system to respond. See
Section 4.4, “Use of CLKEN to Control Bus Cycles,”
for more information.
Address
N Cycle
Write Data
Read Data
N Cycle
CLK
Address
Class Signals
TRANS[1:0]
WDATA[31:0]
(Write)
RDATA[31:0]
(Read)
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