
A-2
Differences Between the ARM7TDMI-S and the ARM7TDMI
Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
Table A.1
ARM7TDMI SSignals and ARM7TDMI Hard Macrocell Equivalents
ARM7TDMI S
Signal
Function
ARM7TDMI
Hard Macrocell
Equivalent
ABORT
1 = memory abort or bus error.
0 = no error.
ABORT
ADDR[31:0]
1
32-bit address output bus, available in the cycle preceding the
memory cycle.
A[31:0]
CFGBIGEND
1 = big-endian configuration.
0 = little-endian configuration.
BIGEND
CLK
2
Master rising edge clock. All inputs are sampled on the rising
edge of CLK. All timing dependencies are from the rising edge of
CLK.
MCLK
CLKEN
3
System memory interface clock enable:
1 = advance the core on rising CLK.
0 = prevent the core advancing on rising CLK.
NWAIT
CPA
4
Coprocessor absent. Tie HIGH when no coprocessor is present.
CPA
CPB
4
Coprocessor busy. Tie HIGH when no coprocessor is present.
CPB
CPnI
Active LOW coprocessor instruction execute qualifier.
nCPI
CPnMREQ
Active LOW memory request signal, pipelined in the preceding
access. This coprocessor interface signal uses the ARM7TDMI-S
output TRANS[1:0] for bus interface design.
nMREQ
CPnOPC
Active LOW opcode fetch qualifier output, pipelined in the preced-
ing access. This coprocessor interface signal uses the
ARM7TDMI-S output PROT[1:0] for bus interface design.
nOPC
CPnTRANS
Active LOW supervisor mode access qualifier output. This copro-
cessor interface signal uses the ARM7TDMI-S output PROT[1:0]
for bus interface design.
nTRANS
CPSEQ
Sequential address signal. This coprocessor interface signal uses
the ARM7TDMI-S output TRANS[1:0] for bus interface design.
SEQ
CPTBIT
Instruction set qualifier output:
1 = Thumb instruction set.
0 = ARM instruction set.
TBIT
DBGACK
Debug acknowledge qualifier output:
1 = processor in debug state (real-time stopped).
0 = normal system state.
DBGACK