參數(shù)資料
型號(hào): ARM7TDMI-S
英文描述: ARM7TDMI-S Microprocessor Core preliminary technical manual 5/00
中文描述: 的ARM7TDMI - S微處理器核的初步技術(shù)手冊(cè)5 / 00
文件頁數(shù): 167/184頁
文件大?。?/td> 1147K
代理商: ARM7TDMI-S
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁當(dāng)前第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁
Behavior of the Program Counter During Debug
Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
B-21
is held off until the core changes into abort mode, and has fetched the
instruction from the abort vector.
A similar sequence follows when an interrupt or any other exception
occurs during a watchpointed memory access. The ARM7TDMI-S core
enters debug state in the mode of the exception. The debugger must
check to see whether an exception has occurred by examining the
current and previous mode (in the CPSR and SPSR), and the value of
the PC. When an exception has taken place, the user should be given
the choice of servicing the exception before debugging.
Entry to debug state when an exception has occurred causes the PC to
be incremented by three instructions rather than four; this case must be
considered in return branch calculation when exiting the debug state. For
example, suppose that an abort has occurred on a watchpointed access
and 10 instructions had been executed to determine this eventuality. You
could use the following sequence to return to program execution.
0 E1A00000; MOV R0, R0
1 E1A00000; MOV R0, R0
0 EAFFFFF0; B 16
This code forces a branch back to the abort vector, causing the
instruction at that location to be refetched and executed.
Note:
After the abort service routine, the instruction that caused
the abort and watchpoint is refetched and executed. This
case triggers the watchpoint again, and the ARM7TDMI-S
core re-enters debug state.
B.8.4 Debug Request
Entry into debug state via a debug request is similar to a breakpoint.
However, unlike a breakpoint, the last instruction has completed
execution and so must not be refetched on exit from debug state.
Therefore you can assume that entry to debug state adds three
addresses to the PC, and every instruction executed in debug state adds
one address.
For example, suppose that the user has invoked a debug request, and
decides to return to program execution straight away. You could use the
following sequence:
相關(guān)PDF資料
PDF描述
ARM946E-S ARM946E-S Microprocessor Core with Cache technical manual 6/01
ARM966E-S ARM966E-S Microprocessor Core preliminary technical manual 6/01
ARS2569 Amplifier. Other
AR2569 Amplifier. Other
ARS4019 Amplifier. Other
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ARM920T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System-on-Chip Platform OS Processor
ARM940T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TECHNICAL REFERENCE MANUAL
ARM946E-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM946E-S Microprocessor Core with Cache technical manual 6/01
ARM966E-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM966E-S Microprocessor Core preliminary technical manual 6/01