
Behavior of the Program Counter During Debug
Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
B-21
is held off until the core changes into abort mode, and has fetched the
instruction from the abort vector.
A similar sequence follows when an interrupt or any other exception
occurs during a watchpointed memory access. The ARM7TDMI-S core
enters debug state in the mode of the exception. The debugger must
check to see whether an exception has occurred by examining the
current and previous mode (in the CPSR and SPSR), and the value of
the PC. When an exception has taken place, the user should be given
the choice of servicing the exception before debugging.
Entry to debug state when an exception has occurred causes the PC to
be incremented by three instructions rather than four; this case must be
considered in return branch calculation when exiting the debug state. For
example, suppose that an abort has occurred on a watchpointed access
and 10 instructions had been executed to determine this eventuality. You
could use the following sequence to return to program execution.
0 E1A00000; MOV R0, R0
1 E1A00000; MOV R0, R0
0 EAFFFFF0; B 16
This code forces a branch back to the abort vector, causing the
instruction at that location to be refetched and executed.
Note:
After the abort service routine, the instruction that caused
the abort and watchpoint is refetched and executed. This
case triggers the watchpoint again, and the ARM7TDMI-S
core re-enters debug state.
B.8.4 Debug Request
Entry into debug state via a debug request is similar to a breakpoint.
However, unlike a breakpoint, the last instruction has completed
execution and so must not be refetched on exit from debug state.
Therefore you can assume that entry to debug state adds three
addresses to the PC, and every instruction executed in debug state adds
one address.
For example, suppose that the user has invoked a debug request, and
decides to return to program execution straight away. You could use the
following sequence: