
The Debug Communications Channel
Rev. A
6-13
Copyright 2000 by LSI Logic Corporation. All rights reserved.
6.7.2.1 Sending a Message to the Debugger
When the processor wishes to send a message to the debugger, it must
check to see if the Comms Data Write Register is free for use. The
processor reads the Debug Comms Control Register to check the status
of the W bit:
If the W bit is cleared, the Comms Data Write Register is cleared.
If the W bit is set, previously written data has not been read by the
debugger. The processor must continue to poll the control register
until the W bit is cleared.
When the W bit is cleared, a message is written by a register transfer to
Coprocessor 14.
Because the data transfer occurs from the processor to the Comms Data
Write Register, the W bit is set in the Debug Comms Control Register.
The debugger sees both the R and W bits when it polls the Debug
Comms Control Register through the JTAG interface. When the debugger
sees that the W bit is set, it can read the Comms Data Write Register
and scan the data out. The action of reading this data register clears the
Debug Comms Control Register W bit. At this point, the communications
process can begin again.
6.7.2.2 Receiving a Message from the Debugger
Transferring a message from the debugger to the processor is similar to
sending a message to the debugger. In this case, the debugger polls the
R bit of the Debug Comms Control Register.
If the R bit is LOW, the Comms Data Read Register is free, and data
can be placed there for the processor to read.
If the R bit is set, previously deposited data has not yet been
collected, so the debugger must wait.
When the Comms Data Read Register is free, data is written there via
the JTAG interface.
The action of this write sets the R bit in the Debug Comms Control
Register.