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| 型號(hào)： | ARM7TDMI-S |
| 英文描述： | ARM7TDMI-S Microprocessor Core preliminary technical manual 5/00 |
| 中文描述： | 的ARM7TDMI - S微處理器核的初步技術(shù)手冊(cè)5 / 00 |
| 文件頁(yè)數(shù)： | 176/184頁(yè) |
| 文件大?。?/td> | 1147K |
| 代理商： | ARM7TDMI-S |
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B-30
Detailed Debug Operation
Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
B.12.1 Hardware Breakpoints
To make a watchpoint unit cause hardware breakpoints (on instruction
fetches):
1.
Program its Address Value Register with the address of the
instruction to be breakpointed.
2.
For an ARM-state breakpoint, program bits [1:0] of the Address Mask
Register to 0b11. For a breakpoint in Thumb state, program bits [1:0]
of the Address Mask Register to 0b01.
3.
Program only the Data Value Register when you require a data-
dependent breakpoint, that is, only when you need to match the
actual instruction code fetched as well as the address. If the data
value is not required, program the Data Mask Register to
0xFFFF.FFFF (all bits to 1); otherwise, program it to 0x00000000.
4.
Program the Control Value Register with PROT[0] = 0.
5.
Program the Control Mask Register with PROT[0] = 0.
6.
When you need to make the distinction between user and non-user
mode instruction fetches, program the PROT[1] value and mask bits,
appropriately.
7.
If required, program the DBGEXT, RANGE, and CHAIN bits in the
same way.
8.
Program the mask bits for all unused control values to 2.
B.12.2 Software Breakpoints
To make a watchpoint unit cause software breakpoints (on instruction
fetches of a particular bit pattern):
1.
Program its Address Mask Register to 0xFFFF.FFFF (all bits set to
1) so that the address is disregarded.
2.
Program the Data Value Register with the particular bit pattern that
has been chosen to represent a software breakpoint.
If you are programming a Thumb software breakpoint, repeat the 16-
bit pattern in both halves of the Data Value Register. For example, if
the bit pattern is 0xDFFF, program 0xDFFF.DFFF. When a 16-bit
instruction is fetched, EmbeddedICE compares only the valid half of
the data bus against the contents of the Data Value Register. In this
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