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Introduction
August 2001 - Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
The library also includes megafunctions or building blocks, which provide
useful functions for developing a system on a chip. Through the Core-
Ware program, you can create a system on a chip uniquely suited to your
applications.
Each core has an associated set of deliverables, including:
RTL simulation models for both Verilog and VHDL environments
A System Verification Environment (SVE) for RTL-based simulation
Synthesis and timing shells
Netlists for full timing simulation
Complete documentation
LSI Logic ToolKit support
LSI Logic's ToolKit provides seamless connectivity between products
from leading electronic design automation (EDA) vendors and LSI Logic's
manufacturing environment. Standard interfaces for formats and lan-
guages such as VHDL, Verilog, Waveform Generation Language (WGL),
Physical Design Exchange Format (PDEF), and Standard Delay Format
(SDF) allow a wide range of tools to interoperate within the LSI ToolKit
environment. In addition to design capabilities, full scan Automatic Test
Pattern Generation (ATPG) tools and LSI Logic's specialized test solu-
tions can be combined to provide high-fault coverage test programs that
assure a fully functional design.
Because your design requirements are unique, LSI Logic is flexible in
working with you to develop your system-on-a-chip CoreWare design.
Three different work relationships are available:
You provide LSI Logic with a detailed specification and LSI Logic per-
forms all design work.
You design some functions while LSI Logic provides you with the
cores and megafunctions, and LSI Logic completes the integration.
You perform the entire design and integration, and LSI Logic provides
the core and associated deliverables.
Whatever the work relationship, LSI Logic's advanced CoreWare meth-
odology and ASIC process technologies consistently produce Right-First-
Time
silicon.