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參數(shù)資料
| 型號： | ARM7TDMI-S |
| 英文描述： | ARM7TDMI-S Microprocessor Core preliminary technical manual 5/00 |
| 中文描述： | 的ARM7TDMI - S微處理器核的初步技術手冊5 / 00 |
| 文件頁數(shù)： | 142/184頁 |
| 文件大?。?/td> | 1147K |
| 代理商： | ARM7TDMI-S |
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A-4
Differences Between the ARM7TDMI-S and the ARM7TDMI
Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
PROT[1:0]
1,8
Protection output, indicates whether the current address is being
accessed as instruction or data, and whether it is being accessed
in a privileged mode or user mode.
nOPC, nTRANS
RDATA[31:0]
9
Unidirectional 32-bit input data bus.
DIN[31:0]
SIZE[1:0]
Indicates the width of the bus transaction to the current address:
00 = 8-bit.
01 = 16-bit.
10 = 32-bit.
11 = not supported.
MAS[1:0]
TCKEN
JTAG interface clock enable:
1 = advance the JTAG logic on rising CLK.
0 = prevent the JTAG logic advancing on rising CLK.
TRANS[1:0]
Next transaction type output bus:
00 = address-only/idle transaction next.
01 = coprocessor register transaction next.
10 = non-sequential (new address) transaction next.
11 = sequential (incremental address) transaction next.
nMREQ, SEQ
WRITE
1
Write access indicator.
nRW
1. All address class signals (ADDR[31:0], WRITE, SIZE[1:0], PROT[1:0], and LOCK) change on the
rising edge of CLK. In a system with a low-frequency clock, it is possible for the signals to change
in the first phase of the clock cycle, which is unlike the ARM7TDMI hard macrocell where they
always change in the last phase of the cycle.
2. CLK is a rising edge clock. It is inverted with respect to the MCLK signal used on the ARM7TDMI
hard macrocell.
3. CLKEN is sampled on the rising edge of CLK. Thus the address class outputs (ADDR[31:0], WRITE,
SIZE[1:0], PROT[1:0], and LOCK) might still change in a cycle in which CLKEN is taken LOW. You
must take this possibility into account when designing a memory system.
4. CPA and CPB are sampled on the rising edge of CLK. They might no longer change in the first
phase of the next cycle, as is possible with the ARM7TDMI hard macrocell.
5. All JTAG signals are synchronous to CLK on the ARM7TDMI-S. There is no asynchronous TCLK
as on the ARM7TDMI hard macrocell. An external synchronizing circuit can be used to generate
TCLKEN when an asynchronous TCLK is required.
6. DBGRQ must be synchronized externally to the macrocell. It is not an asynchronous input as on
the ARM7TDMI hard macrocell.
7. nFIQ and nIRQ are synchronous inputs to the ARM7TDMI-S and are sampled on the rising edge
of CLK. Asynchronous interrupts are not supported.
8. PROT[0] is the equivalent of nOPC, and PROT[1] is the equivalent of nTRANS on the ARM7TDMI
hard macrocell.
9. The ARM7TDMI-S core supports only unidirectional data buses, RDATA[31:0], and WDATA[31:0].
When a bidirectional bus is required, you must implement external bus combining logic.
ARM7TDMI SSignals and ARM7TDMI Hard Macrocell Equivalents
ARM7TDMI S
Signal
Function
ARM7TDMI
Hard Macrocell
Equivalent
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