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參數資料
| 型號： | S5335DK |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁數： | 94/189頁 |
| 文件大小： | 1193K |
| 代理商： | S5335DK |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 94
PCI BURST TRANSFERS
The PCI bus, by default, expects burst transfers to be
executed. To successfully perform a burst transfer,
both the initiator and target must order their burst
address sequence in an identical fashion. There are
two different ordering schemes: linear address incre-
menting and 80486 cache line fill sequencing. The
exact ordering scheme for a bus transaction is defined
by the state of the two least significant AD lines during
the address phase. The decoding for these lines is
shown below:
The S5335 supports both the linear and the cache line
burst ordering. When the S5335 controller is an initia-
tor, it always employs a linear ordering.
Some accesses to the S5335 controller (as a target)
can not be burst transfers. For example, the S5335
does not allow burst transfers when accesses are
made to the configuration or operation registers
(including the FIFO as a target). Attempts to perform
burst transfers to these regions cause STOP# to be
asserted during the first data phase. The S5335 com-
pletes the initial data phase successfully, but asserting
STOP# indicates that the next access needs to be a
completely new cycle. Accesses to memory or I/O
regions defined by the Base Address Registers 1-4
may be bursts, if desired.
PCI Read Transfers
The S5335 responds to PCI bus memory or I/O read
transfers when it is selected (target). As a PCI bus ini-
tiator, the S5335 controller may also produce PCI bus
memory read operations.
Figure 46 depicts the fastest burst read transfer possi-
ble for the PCI bus. The timings shown in Figure 46
are representative of the S5335 as a PCI initiator with
a fast, zero-wait-state memory target. The signals
driven by the S5335 during the transfer are FRAME#,
C/BE[3:0]#, and IRDY#. The signals driven by the tar-
get are DEVSEL# and TRDY#. AD[31:0] are driven by
both the target and initiator during read transactions
(only one during any given clock). Clock period 2 is a
required bus turn-around clock which ensures bus
contention between the initiator and target does not
occur.
Targets drive DEVSEL# and TRDY# after the end of
the address phase (boundary of clock periods 1 and 2
of Figure 46). TRDY# is not driven until the target can
provide valid data for the PCI read. When the S5335
becomes the PCI initiator, it attempts to perform sus-
tained zero-wait state burst reads until one of the
following occurs:
The memory target aborts the transfer
PCI bus grant (GNT#) is removed
The PCI to Add-On FIFO becomes full
A higher priority (Add-On to PCI) S5335 trans-
fer is pending (if programmed for priority)
The read transfer byte count reaches zero
Bus mastering is disabled from the Add-On
interface
Figure 46. Zero Wait State Burst Read PCI Bus Transfer (S5335 as Initiator)
AD[1:0]
Burst Order
0 0
Linear sequence
0 1
Reserved
1 0
Cacheline Wrap Mode
1 1
Reserved
1 2
3
4 5
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
TRDY#
DEVSEL#
ADDRESS
DATA (2)
DATA (3)
(T)
(T)
(T)
DATA (1)
BYTE EN (2)
BYTE EN (3)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
BYTE ENABLES (1)
BUS COMMAND
(I)
(T)
(I)
(I)
(I)
(T)
6
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相關代理商/技術參數 |
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