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參數(shù)資料
| 型號： | S5335DK |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁數(shù)： | 138/189頁 |
| 文件大小： | 1193K |
| 代理商： | S5335DK |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 138
7. Enable Bus Mastering. Once steps 1-6 are com-
pleted, the FIFO may operate as a PCI bus
master. Read and write bus master operation
may be independently enabled or disabled.
The order of the tasks listed above is not particularly
important. It is recommended that bus mastering be
enabled as the last step. Some applications may
choose to leave bus mastering enabled and start
transfers by writing a non-zero value to the transfer
count registers. This also works, provided the entire
transfer count is written in a single access. As a num-
ber of the configuration bits and the two enable bits
are all in the MCSR register, it may be most efficient
for the FIFO configuration bits to be set with the same
register access that enables bus mastering.
If interrupts are enabled, a host interrupt service rou-
tine is also required. The service routine determines
the source of the interrupt and resets the interrupt. As
mailbox registers may also be configured to generate
interrupts, the exact source of the interrupt is indicated
in the PCI Interrupt Control/Status Register (INTCSR).
Typically, the interrupt service routine is used to setup
the next transfer by writing new addresses and trans-
fer counts, but some applications may also require
other actions. If read transfer or write transfer com-
plete interrupts are enabled, master and target abort
interrupts are automatically enabled. These indicate a
transfer error has occurred. Writing a one to these bits
clears the corresponding interrupt.
Add-On Initiated FIFO Bus Mastering Setup For Add-
On initiated bus mastering, the Add-On sets up the
S5335 to perform bus master transfers. The following
tasks must be completed to setup FIFO bus
mastering:
1. Define transfer count abilities. For Add-On initi-
ated bus mastering, transfer counts may be either
enabled or disabled. Transfer counts for read and
write operations cannot be individually enabled.
2. Define interrupt capabilities. The PCI to Add-On
and/or Add-On to PCI FIFO can generate an
interrupt to the Add-On when the transfer count
reaches zero (if transfer counts are enabled).
3. Reset FIFO flags. This may not be necessary, but
if the state of the FIFO flags is not known, they
should be initialized.
4. Define FIFO management scheme. These bits
define what FIFO condition must exist for the PCI
bus request (REQ#) to be asserted by the S5335.
This must be programmed through the PCI
interface.
MCSR
Bit 14
Enable PCI to Add-On FIFO bus mas-
tering
MCSR
Bit 10
Enable Add-On to PCI FIFO bus mas-
tering
INTCSR
Bit 21
Target abort caused interrupt
INTCSR
Bit 20
Master abort caused interrupt
INTCSR
Bit 19
Read transfer complete caused inter-
rupt
INTCSR
Bit 18
Write transfer complete caused inter-
rupt
AGCSTS
Bit 28
Enable transfer count for read and
write bus master transfers
AINT
Bit
15 Enable interrupt on read transfer
count equal zero
AINT
Bit 14
Enable interrupt on write transfer count
equal zero
AGCSTS
Bit 25
Reset Add-On to PCI FIFO flags
AGCSTS
Bit 26
Reset PCI to Add-On FIFO flags
MCSR
Bit 13
PCI to Add-On FIFO management
scheme
MCSR
Bit 9
Add-On to PCI FIFO management
scheme
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