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參數(shù)資料
| 型號(hào)： | S5335DK |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁(yè)數(shù)： | 113/189頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335DK |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 113
Some nv memories may contain Expansion ROM
BIOS code for use by the host software. During initial-
ization, the Expansion BIOS is located within system
memory. The starting location of the nv memory is
stored in the Expansion ROM Base Address Register
in the S5335 PCI Configuration Registers. A PCI read
from this region results in the S5335 performing four
consecutive byte access to the nv memory device.
Writes to the nv memory are not allowed by writing to
this region. Writes to the nv memory must be per-
formed as described below.
The S5335 contains two latches within the MCSR reg-
ister to control and access the NVRAM. One is an 8 bit
latch called the NVRAM Address/Data Register which
is used to hold NVRAM address and data information.
The other is a 3 bit latch called the NVRAM Access
Control Register which is used to direct the address
and data information and to control the NVRAM itself.
Reading or writing to the NVRAM is performed through
bits D31:29 of this register. These bits are enable and
decode controls rather than a command or instruction
to be executed. D31 of this register is the primary
enable bit which allows all accesses to occur. When
written to a ‘1’, D31 enables the decode bits D30 and
D29 to direct the data contained in the address/data
latch, D23:16, to the low address, high address or data
latches. D31 should be thought of as “opening a door”
where as long as D31 = 1, then the door is open for
address or data information to be altered. The table on
page 5-16 of the S5335 data book shows the D31:29
bit combinations for reading, writing, and loading ad-
dress/data information. Additionally, D31 doubles as
an S5335 status bit. A ‘1’ indicates that the S5335 is
currently busy reading or writing to the NVRAM. A ‘0’
indicates a complete or inactive state.
For the examples below, we will assume the S5335 is
I/O mapped with a base address of FC00h. These
examples will read one byte of the Vendor ID and write
one byte to the Vendor ID.
This example will write 1 byte from NVRAM location 0040h and read it back:
In
Out
Out
Out
Out
Out
Out
Out
In
Out
In
In
FC00h + 3Fh
(offset of NVRAM Access Control Register) until
D31 = 0
(not busy).
FC00h + 3FH
an
80h
(CMD to load the low address byte). This sets decode bits and opens door for low address
latch.
FC00h + 3Eh
(offset of Address/Data Register)
40h
(the low byte of the address desired) 40h goes into latch but is
not latched yet.
FC00h + 3Fh
an A0h (CMD to load the high address byte). This latches the low address through changing the
decode bits and opens the door for the high address latch.
FC00h + 3Eh
a
00h
(the high byte of the address desired). 00h goes into the latch but is not latched yet.
FC00h + 3Fh
an
00h
(inactive CMD). This latches the high address through the disabling D31, ‘closes the door’.
FC00h + 3Eh
DATA
(the data byte to be written). DATA byte goes into the latch but is not latched yet.
FC00h + 3Fh
a
C0h
(CMD to write the data byte). This latches the data byte through changing the decode bits and
begins to write NVRAM data operation.
FC00h + 3Fh
until
D31
= 0
(not busy).
FC00h + 3Fh
an
E0h
(CMD to read the address latched).
FC00h + 3Fh
until
D31 = 0
(not busy).
FC00h + 3Eh
the
data
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5335QF | PCI Bus Controller, 3.3V |
| S5335QFAAB | PCI Bus Controller, 3.3V |
| S5566B | General Purpose Rectifier(通用整流器) |
| S5566G | General Purpose Rectifier(通用整流器) |
| S5566J | GENERAL PURPOSE RECTIFIER APPLICATIONS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5335QF | 制造商:AppliedMicro 功能描述: |
| S5335QFAAB | 制造商:AppliedMicro 功能描述:PCI Bus Controller |
| S533-M04-F13A-E | 制造商:UNICORP 功能描述: |
| S-533-M04-F13-F | 制造商:UNICORP 功能描述: |
| S533-M04-F13-F | 制造商:UNICORP 功能描述: |
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