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參數(shù)資料
| 型號(hào)： | S5335DK |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁數(shù)： | 5/189頁 |
| 文件大小： | 1193K |
| 代理商： | S5335DK |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 5
MAILBOX BUS INTERFACE .............................................................................................................................. 108
Mailbox Interrupts .......................................................................................................................................... 111
FIFO BUS INTERFACE ....................................................................................................................................... 111
FIFO Direct Access Inputs ............................................................................................................................. 111
FIFO Status Signals ...................................................................................................................................... 111
FIFO Control Signals ..................................................................................................................................... 111
PASS-THRU BUS INTERFACE .......................................................................................................................... 111
Pass-Thru Status Indicators .......................................................................................................................... 111
Pass-Thru Control Inputs ............................................................................................................................... 111
NON-VOLATILE MEMORY INTERFACE ........................................................................................................... 112
Non-Volatile Memory Interface Signals ......................................................................................................... 112
Accessing Non-Volatile Memory .................................................................................................................... 112
nv Memory Device Timing Requirements ...................................................................................................... 115
MAILBOX OVERVIEW ........................................................................................................................................ 117
FUNCTIONAL DESCRIPTION ............................................................................................................................ 117
Mailbox Empty/Full Conditions ...................................................................................................................... 118
Mailbox Interrupts .......................................................................................................................................... 118
Add-On Outgoing Mailbox 4, Byte 3 Access ................................................................................................. 119
BUS INTERFACE ................................................................................................................................................ 119
PCI Bus Interface .......................................................................................................................................... 119
Add-On Bus Interface .................................................................................................................................... 119
8-Bit and 16-Bit Add-On Interfaces ................................................................................................................ 120
CONFIGURATION ............................................................................................................................................... 120
Mailbox Status ............................................................................................................................................... 120
Mailbox Interrupts .......................................................................................................................................... 121
S5335 FIFO OVERVIEW ..................................................................................................................................... 124
FUNCTIONAL DESCRIPTION ............................................................................................................................ 124
FIFO Buffer Management and Endian Conversion ....................................................................................... 124
FIFO Advance Conditions ............................................................................................................................. 124
Endian Conversion ........................................................................................................................................ 125
64-Bit Endian Conversion .............................................................................................................................. 126
Add-On FIFO Status Indicators ..................................................................................................................... 127
Add-On FIFO Control Signals ........................................................................................................................ 127
PCI Bus Mastering with the FIFO .................................................................................................................. 127
Add-On Initiated Bus Mastering ..................................................................................................................... 127
PCI Initiated Bus Mastering ........................................................................................................................... 128
Address and Transfer Count Registers ......................................................................................................... 128
Bus Mastering FIFO Management Schemes ................................................................................................ 128
FIFO Bus Master Cycle Priority ..................................................................................................................... 129
FIFO Generated Bus Master Interrupts ......................................................................................................... 129
BUS INTERFACE ................................................................................................................................................ 129
FIFO PCI Interface (Target Mode) ................................................................................................................. 129
FIFO PCI Interface (Initiator Mode) ............................................................................................................... 130
FIFO PCI Bus Master Reads ......................................................................................................................... 132
FIFO PCI Bus Master Writes ......................................................................................................................... 132
Add-On Bus Interface .................................................................................................................................... 132
Add-On FIFO Register Accesses .................................................................................................................. 132
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