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參數(shù)資料
| 型號(hào)： | S5335DK |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁(yè)數(shù)： | 49/189頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335DK |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 49
Expansion ROM Base Address Register (XROM)
The expansion base address ROM register provides a
mechanism for assigning a space within physical
memory for an expansion ROM. Access from the PCI
bus to the memory space defined by this register will
cause one or more accesses to the S5335 controllers’
external BIOS ROM (or nvRAM) interface. Since PCI
bus accesses to the ROM may be 32 bits wide,
repeated operations to the ROM are generated by the
S5335 and the wider data is assembled internal to the
S5335 controller and then transferred to the PCI bus
by the S5335.
Figure 19. Expansion ROM Base Address Register
Register Name:
Expansion ROM Base Address
Address Offset:
30h
Power-up value:
00000000h
Boot-load:
External nvRAM offset 70h
Attribute:
bits 31:11, bit 0 Read/Write; bits 10:1
Read Only
Size:
32 bits
Table 41. Expansion ROM Base Address Register
Bit
Description
31:11
Expansion ROM Base Address Location. These bits are used to position the decoded region in memory space. Only
bits which return a 1 after being written as 1 are usable for this purpose. These bits are individually enabled by the
contents sourced from the external boot memory (EPROM or nvRAM). The desired size for the ROM memory is
determined by writing all ones to this register and then reading back the contents. The number of bits returned as
zeros, in order from least significant to most significant bit, indicates the size of the expansion ROM. This controller
limits the expansion ROM area to 64K bytes. The allowable returned values after all ones are written to this register
are shown in TTable 42.
10:1
Reserved. All zeros.
0
Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit. When this bit is
set, the decoder is enabled; when this bit is zero, the decoder is disabled. It is required that the PCI command regis-
ter also have the memory decode enabled for this bit to have an effect.
31
0
0
0
1
10
Bit
Value
Address Decode
Enable (RW)
0=Disabled
1=Enabled
Reserved (RO)
Programmable (R/W)
11
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