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參數資料
| 型號： | S5335DK |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁數： | 132/189頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335DK |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 132
FIFO PCI Bus Master Reads
For PCI read transfers (filling the PCI to Add-On
FIFO), read cycles are performed until one of the fol-
lowing occurs:
- Bus Master Read Transfer Count Register
(MRTC), if used, reaches zero
- The PCI to Add-On FIFO is full
- GNT# is removed by the PCI bus arbiter
- AMREN is deasserted
If the transfer count is not zero, GNT# remains
asserted, and AMREN is asserted, the FIFO continues
to read data from the PCI bus until there are no empty
locations in the PCI to Add-On FIFO. If the Add-On
can empty the FIFO as quickly as it can be filled from
the PCI bus, very long bursts are possible. The S5335
deasserts REQ# when it completes the access to fill
the last location in the FIFO. Once REQ# is deas-
serted, it will not be reasserted until the FIFO
management condition is met.
FIFO PCI Bus Master Writes
For PCI write transfers (emptying the Add-On to PCI
FIFO), write cycles are performed until one of the fol-
lowing occurs:
- Bus Master Write Transfer Count Register
(MWTC), if used, reaches zero
- The Add-On to PCI FIFO is empty
- GNT# is removed by the PCI bus arbiter
- AMWEN is deasserted
If the transfer count is not zero, GNT# remains
asserted, and AMWEN is asserted, The FIFO contin-
ues to write data to the PCI bus until there are is no
data in the Add-On to PCI FIFO. If the Add-On can fill
the FIFO as quickly as it can be emptied to the PCI
bus, very long bursts are possible. The S5335 deas-
serts REQ# when it completes the access to transfer
the last data in the FIFO. Once REQ# is deasserted, it
will not be reasserted until the FIFO management con-
dition is met.
Add-On Bus Interface
The FIFO register may be accessed in two ways from
the Add-On interface. It can be accessed through nor-
mal register accesses or directly with the RDFIFO#
and WRFIFO# inputs. In addition, the FIFO register
can also be accessed synchronous to BPCLK. The
Add-On interface also supports datapaths which are
not 32-bits. The method used to access the FIFO from
the Add-On interface is independent of whether the
FIFO is a PCI target or a PCI initiator.
Add-On FIFO Register Accesses
The FIFO may be accessed from the Add-On interface
through the Add-On FIFO Port Register (AFIFO) read
or write. This is offset 20h in the Add-On Operation
Registers. This register is accessed synchronous to
BPCLK. To access the FIFO as a normal Add-On
Operation Register, ADR[6:2], BE[3:0]#, SELECT#,
and RD# or WR# are required.
Figure 81 shows a synchronous FIFO register burst
access. SELECT# must meet setup and hold times
relative to the rising edge of BPCLK. RD# and
SELECT# both asserted enables the DQ outputs, and
the first data location (data 0) in the FIFO is driven on
to the bus. The FIFO address and the byte enables
must be valid before valid data is driven onto the DQ
bus. Data 0 remains valid until the next rising edge of
BPCLK. The rising edge of BPCLK causes the FIFO
pointer to advance to the next location (data 1). The
next rising edge of BPCLK also advances the FIFO
pointer to the next location (data 2). The status outputs
reflect the FIFO condition after it advances, and are
updated off of the rising edge of BPCLK. When RD# or
SELECT# is deasserted, the DQ bus floats. The next
time a valid FIFO access occurs and RD# and
SELECT# are asserted, data 2 is presented on the DQ
bus (as there was no BPCLK edge to advance the
FIFO).
Add-On FIFO Direct Access Mode
Instead of generating an address, byte enables,
SELECT# and a RD# or WR# strobe for every FIFO
access, the S5335 allows a simple, direct access
mode. Using RDFIFO# and WRFIFO# is functionally
identical to performing a standard AFIFO Port Register
access, but requires less logic to implement. Accesses
to the FIFO register using the direct access signals are
always 32-bits wide. The only exception to this is when
the MODE pin is configured for 16-bit operation. In this
situation, all accesses are 16-bits wide. The RD# and
WR# inputs must be inactive when RDFIFO# or
WRFIFO# is active. The ADR[6:2] and BE[3:0]# inputs
are ignored. RDFIFO# and WRFIFO# act as enables
with BPCLK acting as the clock. A Synchronous inter-
face allows higher data rates.
Figure 82 shows a synchronous FIFO register direct
burst access using RDFIFO#. RDFIFO# acts as an
enable and the first data location (data 0) in the FIFO
is driven on to the bus when RDFIFO# is asserted.
Data 0 remains valid until the next rising edge of
BPCLK. The rising edge of BPCLK causes the FIFO
pointer to advance to the next location (data 1). The
next rising edge of BPCLK advances the FIFO pointer
to the next location (data 2). The status outputs reflect
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