- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374668 > S5335DK (Applied Micro Circuits Corp.) PCI Bus Controller, 3.3V PDF資料下載
參數(shù)資料
| 型號(hào)： | S5335DK |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁(yè)數(shù)： | 119/189頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335DK |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)當(dāng)前第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)
S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 119
Add-On Outgoing Mailbox 4, Byte 3 Access
PCI incoming mailbox 4, byte 3 (Add-On outgoing
mailbox 4, byte 3) does not function exactly like the
other mailbox bytes. When an a serial nv memory boot
device or no external boot device is used, the S5335
pins EA7:0 are redefined to provide direct external
access to Add-On outgoing mailbox 4, byte 3. EA8 is
redefined to provide a load clock which may be used
to generate a PCI interrupt. The pins are redefined as
follows:
If the S5335 is programmed to generate a PCI inter-
rupt (INTA#), on an Add-On write to outgoing mailbox
4, byte 3, a rising edge on EMBCLK generates a PCI
interrupt. The bits EMB7:0 can be read by the PCI bus
interface by reading the PCI incoming mailbox 4, byte
3. These bits are useful to indicate various conditions
which may have caused the interrupt.
When using the S5335 with a byte-wide boot device,
the capability to generate PCI interrupts with Add-On
hardware does not exist. In this configuration, PCI
incoming mailbox 4, byte 3 (Add-On incoming mailbox
4, byte 3) cannot be used to transfer data from the
Add-On - it always returns zeros when read from the
PCI bus. This mailbox byte is sacrificed to allow the
added functionality provided when a byte-wide boot
device is not used.
BUS INTERFACE
The mailboxes appear on the Add-On and PCI bus
interfaces as eight operation registers. Four are outgo-
ing mailboxes, four are incoming mailboxes. The
mailboxes may be used to generate interrupts to each
of the interfaces. The following sections describe the
Add-On and PCI bus interfaces for the mailbox
registers.
PCI Bus Interface
The mailboxes are only accessible with the S5335 as
a PCI target. The mailbox operation registers do not
support burst accesses by an initiator. A PCI initiator
attempting to burst to the mailbox registers causes the
S5335 to respond with a target disconnect with data.
PCI writes to full outgoing mailboxes overwrite data
currently in that the mailbox. PCI reads from empty
incoming mailboxes return the data that was previ-
ously contained in the mailbox. Neither of these
situations cause a target retry or abort.
PCI incoming and outgoing mailbox interrupts are
enabled in the Interrupt Control/Status Register
(INTCSR). The mailboxes can generate a PCI inter-
rupt (INTA#) under two conditions (individually
enabled). For an incoming mailbox full interrupt, INTA#
is asserted on the PCI clock rising edge after the Add-
On mailbox write completes. For an outgoing mailbox
empty interrupt, INTA# is asserted on the PCI clock
rising edge after the Add-On mailbox read completes
(the rising edge of RD#). INTA# is deasserted on the
next PCI clock rising edge after the PCI access to
clear the mailbox interrupt completes (TRDY#
deasserted).
Add-On Bus Interface
The Add-On mailbox interface behaves similar to the
PCI bus interface. Add-On writes to full outgoing mail-
boxes overwrite data currently in that mailbox. PCI
reads from empty incoming mailboxes return the data
that was previously contained in the mailbox.
Add-On incoming and outgoing mailbox interrupts are
enabled in the Add-On Interrupt Control/Status Regis-
ter (AINT). The mailboxes can generate the Add-On
IRQ# interrupt under two conditions (individually
enabled). For an incoming mailbox full interrupt, IRQ#
is asserted one PCI clock period after the PCI mailbox
write completes (TRDY# deasserted). For an outgoing
mailbox empty interrupt, IRQ# is asserted one PCI
clock period after the PCI mailbox read completes
(TRDY# deasserted). IRQ# is deasserted immediately
when the Add-On clears the mailbox interrupt.
When the S5335 is used with a serial nv memory boot
device or no external boot device, the device pins
EA8:0 are redefined. EA7:0 become EMB7:0 data
inputs and EA8 becomes EMBCLK, a load clock. This
configuration allows the Add-On to generate PCI inter-
rupts with a low-to-high transition on EMBCLK. The
PCI incoming mailbox interrupt must be enabled and
set for mailbox 4, byte3 in the PCI Interrupt Control/
Status Register (INTCSR). EMBCLK should begin
high and be pulsed low, then high to be recognized.
The rising edge of EMBCLK generates the interrupt.
The rising edge of EMBCLK also latches in the values
on EMB7:0. The S5335 interrupt logic must be cleared
(INTA# deasserted) through INTCSR before further
EMBCLK interrupts are recognized.
Signal Pin
Add-On Outgoing Mailbox
EA0/EMB0
EA1/EMB1
EA2/EMB2
EA3/EMB3
EA4/EMB4
EA5/EMB5
EA6/EMB6
EA7/EMB7
EA8/EMBCLK
Mailbox 4, bit 24
Mailbox 4, bit 25
Mailbox 4, bit 26
Mailbox 4, bit 27
Mailbox 4, bit 28
Mailbox 4, bit 29
Mailbox 4, bit 30
Mailbox 4, bit 31
Mailbox 4, byte 3 load clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5335QF | PCI Bus Controller, 3.3V |
| S5335QFAAB | PCI Bus Controller, 3.3V |
| S5566B | General Purpose Rectifier(通用整流器) |
| S5566G | General Purpose Rectifier(通用整流器) |
| S5566J | GENERAL PURPOSE RECTIFIER APPLICATIONS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5335QF | 制造商:AppliedMicro 功能描述: |
| S5335QFAAB | 制造商:AppliedMicro 功能描述:PCI Bus Controller |
| S533-M04-F13A-E | 制造商:UNICORP 功能描述: |
| S-533-M04-F13-F | 制造商:UNICORP 功能描述: |
| S533-M04-F13-F | 制造商:UNICORP 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。