- 您現在的位置：買賣IC網 > PDF目錄374668 > S5335DK (Applied Micro Circuits Corp.) PCI Bus Controller, 3.3V PDF資料下載
參數資料
| 型號： | S5335DK |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁數： | 129/189頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335DK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁當前第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁
S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 129
the management scheme and finishes transferring the
data. The second case is when the S5335 is config-
ured for Add-On initiated bus mastering with transfer
counts disabled. In this situation, the FIFO manage-
ment scheme must be set to request the PCI bus
when one or more locations are full. AMREN and
AMWEN may be used to implement a specific FIFO
management scheme.
FIFO Bus Master Cycle Priority
In many applications, the FIFO is used as a PCI initia-
tor performing both PCI reads and writes. This
requires a priority scheme be implemented. What hap-
pens if the FIFO condition for initiating a PCI read and
a PCI write are both met
Bits D12 and D8 in the Bus Master Control/Status
Register (MCSR) control the read and write cycle pri-
ority, respectively. If these bits are both set or both
clear, priority alternates, beginning with a read cycle. If
the read priority is set and the write priority is clear,
read cycles take priority. If the write priority is set and
the read priority is clear, write cycles take priority. Pri-
ority arbitration is only done when neither FIFO has
control of the PCI bus (the PCI to Add-On FIFO would
never interrupt an Add-On to PCI FIFO transfer).
FIFO Generated Bus Master Interrupts
Interrupts may be generated under certain conditions
from the FIFO. If PCI initiated bus mastering is used,
INTA# is generated to the PCI interface. If Add-On ini-
tiated bus mastering is used, IRQ# is generated to the
Add-On interface. Interrupts may be disabled.
FIFO Interrupts may be generated from one or more of
the following during bus mastering: read transfer count
reaches zero, write transfer count reaches zero, or an
error occurs during bus mastering. Error conditions
include a target or master abort on the PCI bus. Inter-
rupts on PCI error conditions are only enabled if one or
both of the transfer count interrupts are enabled.
The Add-On Interrupt Control/Status Register (AINT)
or the Interrupt Control Status Register (INTCSR) indi-
cates the interrupt source. The interrupt service
routine may read these registers to determine what
action is required. As mailboxes are also capable of
generating interrupts, this must also be considered in
the service routine. Interrupts are also cleared through
these registers.
BUS INTERFACE
The S5335 FIFO may be accessed from the Add-On
interface or the PCI interface. Add-On FIFO control
and status signals allow a simple interface to the FIFO
with either an Add-On CPU or programmable logic.
The following section describes the PCI and Add-On
interface behavior and hardware interface.
FIFO PCI Interface (Target Mode)
The S5335 FIFO may act as a standard PCI target.
FIFO empty/full status may be determined by the PCI
initiator by reading the status bits in the PCI Bus Mas-
ter Control/Status Register (MCSR).
The FIFO occupies a single 32-bit register location
within the PCI Operation Registers.
A PCI initiator
may not perform burst accesses to a FIFO as it is a
single address.
Each data phase of a burst causes
the PCI initiator to increment its address counter (even
though only the first address is driven at the beginning
of the burst). The initiator keeps track of the current
address in case a disconnect occurs. This allows the
initiator to continue the burst from where the discon-
nect occurred. If the S5335 FIFO initiated a disconnect
during a PCI burst to the FIFO register, the burst would
be resumed at an address other than the FIFO loca-
tion (because the initiator address counter has
incremented). The S5335 always signals a disconnect
if a burst to any PCI Operation Register is attempted.
Because the PCI to Add-On FIFO and the Add-On to
PCI FIFO occupy a single location within the PCI and
Add-On Operation Registers, which FIFO is accessed
is determined by whether the access is a read or write.
This means that once data is written into the FIFO, the
value written cannot be read back.
For PCI reads from the Add-On to PCI FIFO, the
S5335 asserts TRDY# and completes the PCI cycle
(Figure 77). If the PCI bus attempts to read an empty
FIFO, the S5335 immediately issues a disconnect with
retry (Figure 78). The Add-On to PCI FIFO status indi-
cators change one PCI clock after a PCI read.
For PCI writes to the PCI to Add-On, the S5335
asserts TRDY# and completes the PCI cycle (Figure
79). If the PCI bus attempts to write a full FIFO, the
S5335 immediately issues a disconnect with retry (Fig-
ure 80). The PCI to Add-On FIFO status indicators
change one PCI clock after a PCI write.
相關PDF資料 |
PDF描述 |
|---|---|
| S5335QF | PCI Bus Controller, 3.3V |
| S5335QFAAB | PCI Bus Controller, 3.3V |
| S5566B | General Purpose Rectifier(通用整流器) |
| S5566G | General Purpose Rectifier(通用整流器) |
| S5566J | GENERAL PURPOSE RECTIFIER APPLICATIONS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| S5335QF | 制造商:AppliedMicro 功能描述: |
| S5335QFAAB | 制造商:AppliedMicro 功能描述:PCI Bus Controller |
| S533-M04-F13A-E | 制造商:UNICORP 功能描述: |
| S-533-M04-F13-F | 制造商:UNICORP 功能描述: |
| S533-M04-F13-F | 制造商:UNICORP 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。