- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374668 > S5335DK (Applied Micro Circuits Corp.) PCI Bus Controller, 3.3V PDF資料下載
參數(shù)資料
| 型號： | S5335DK |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁數(shù)： | 127/189頁 |
| 文件大小： | 1193K |
| 代理商： | S5335DK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁當(dāng)前第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁
S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 127
Add-On FIFO Status Indicators
The Add-On interface implements FIFO status pins to
indicate the full and empty conditions of the PCI to
Add-On and Add-On to PCI FIFOs. These may be
used by the Add-On to allow data transfers between
the FIFO and memory, a peripheral, or even a cas-
caded external FIFO. The RDEMPTY and WRFULL
status outputs are always available to the Add-On.
Additional status signals are multiplexed with the byte-
wide, non-volatile memory interface pins. If the S5335
is configured for Add-On initiated bus mastering, these
status signals also become available to the Add-On.
FIFO status is also indicated by bits in the Add-On
General Control/Status and Bus Master Control/Status
Registers. The table below lists all FIFO status outputs
and their functions.
1. These signals are only available when a serial non-volatile mem-
ory is used and the device is configured for Add-On initiated bus
mastering.
Add-On FIFO Control Signals
The Add-On interface implements FIFO control pins to
manipulate the S5335 FIFOs. These may be used by
Add-On to control data transfer between the FIFO and
memory, a peripheral, or even a cascaded external
FIFO. The RDFIFO# and WRFIFO# inputs are always
available. These pins allow direct access to the FIFO
without generating a standard Add-On register access
using RD#, WR#, SELECT#, address pins and the
byte enables.
Additional control signals are multiplexed with the
byte-wide, non-volatile memory interface pins. If a
serial non-volatile memory is used and the S5335 is
configured for Add-On initiated bus mastering, these
control signals also become available. For PCI initi-
ated bus mastering, AMREN, AMWEN, FRC#, and
FWC# functionality is always available through bits in
the Bus Master Control/Status and Add-On General
Control/Status Registers. The FIFO control inputs are
listed below.
1. These signals are only available when a serial non-volatile mem-
ory is used and the S5335 is configured for Add-On initiated bus
mastering.
PCI Bus Mastering with the FIFO
The S5335 may initiate PCI bus cycles through the
FIFO interface. The S5335 allows blocks of data to be
transferred to and from the Add-On by specifying a
source/destination address on the PCI bus and a
transfer byte count. This DMA capability allows data to
be transferred across the PCI bus without host CPU
intervention.
Initiating a bus master transfer requires programming
the appropriate address registers and transfer byte
counts. This can be done from either the PCI interface
or the Add-On interface. Initiating bus master transfers
from the add-on is advantageous because the host
CPU does not have to intervene for the S5335 to
become a PCI Initiator. At the end of a transfer the
S5335 may generate an interrupt to either the PCI bus
(for PCI initiated transfers) or Add-On interface (for
Add-On initiated transfers).
Add-On Initiated Bus Mastering
If bit 7 in location 45h of an external serial non-volatile
memory is zero, the Master Read Address Register
(MRAR), Master Write Address Register (MWAR),
Master Read Transfer Count (MRTC), and Master
Write Transfer Count (MWTC) are accessible only
from the Add-On interface. Add-On initiated bus mas-
tering is not possible when a byte-wide boot device is
used due to shared device pins. When configured for
Add-On initiated bus mastering, the S5335 transfers
data until the transfer count reaches zero, or it may be
configured to ignore the transfer count.
Signal
Function
RDEMPTY
Indicates empty condition of the PCI to
Add-On FIFO
WRFULL
Indicates full condition of the Add-On to
PCI FIFO
FRF
Indicates full condition of the PCI to Add-
On FIFO
1
FWE
Indicates the empty condition of the Add-
On to PCI FIFO
1
Signal
Function
RDFIFO#
Reads data from the PCI to Add-On FIFO
WRFIFO#
Writes data into the Add-On to PCI FIFO
FRC#
Reset PCI to Add-On FIFO pointers and
status indicators
1
FWC#
Reset Add-On to PCI FIFO pointers and
status indicators
1
AMREN
Enable bus mastering for Add-On initiated
PCI reads
1
AMWEN
Enable bus mastering for Add-On initiated
PCI writes
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5335QF | PCI Bus Controller, 3.3V |
| S5335QFAAB | PCI Bus Controller, 3.3V |
| S5566B | General Purpose Rectifier(通用整流器) |
| S5566G | General Purpose Rectifier(通用整流器) |
| S5566J | GENERAL PURPOSE RECTIFIER APPLICATIONS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5335QF | 制造商:AppliedMicro 功能描述: |
| S5335QFAAB | 制造商:AppliedMicro 功能描述:PCI Bus Controller |
| S533-M04-F13A-E | 制造商:UNICORP 功能描述: |
| S-533-M04-F13-F | 制造商:UNICORP 功能描述: |
| S533-M04-F13-F | 制造商:UNICORP 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。