
Rev. 1.00 Mar. 02, 2006 Page xvii of xl
11.5.1
TCNT Count Timing ........................................................................................ 316
11.5.2
Timing of CMFA and CMFB Setting at Compare-Match ................................ 317
11.5.3
Timing of Timer Output at Compare-Match..................................................... 317
11.5.4
Timing of Counter Clear at Compare-Match .................................................... 318
11.5.5
TCNT External Reset Timing ........................................................................... 318
11.5.6
Timing of Overflow Flag (OVF) Setting .......................................................... 319
11.6
TMR_0 and TMR_1 Cascaded Connection...................................................................... 320
11.6.1
16-Bit Count Mode ........................................................................................... 320
11.6.2
Compare-Match Count Mode ........................................................................... 320
11.7
TMR_Y and TMR_X Cascaded Connection .................................................................... 321
11.7.1
16-Bit Count Mode ........................................................................................... 321
11.7.2
Compare-Match Count Mode ........................................................................... 321
11.7.3
Input Capture Operation ................................................................................... 322
11.8
Interrupt Sources...............................................................................................................324
11.9
Usage Notes ...................................................................................................................... 325
11.9.1
Conflict between TCNT Write and Counter Clear............................................ 325
11.9.2
Conflict between TCNT Write and Count-Up .................................................. 325
11.9.3
Conflict between TCOR Write and Compare-Match........................................ 326
11.9.4
Conflict between Compare-Matches A and B .................................................. 326
11.9.5
Switching of Internal Clocks and TCNT Operation.......................................... 327
11.9.6
Mode Setting with Cascaded Connection ......................................................... 329
11.9.7
Module Stop Mode Setting ............................................................................... 329
Section 12 Watchdog Timer (WDT)..................................................................331
12.1
Features............................................................................................................................. 331
12.2
Input/Output Pins .............................................................................................................. 333
12.3
Register Descriptions ........................................................................................................ 333
12.3.1
Timer Counter (TCNT)..................................................................................... 333
12.3.2
Timer Control/Status Register (TCSR)............................................................. 334
12.4
Operation .......................................................................................................................... 338
12.4.1
Watchdog Timer Mode ..................................................................................... 338
12.4.2
Interval Timer Mode ......................................................................................... 339
12.5
Interrupt Sources...............................................................................................................340
12.6
Usage Notes ...................................................................................................................... 340
12.6.1
Notes on Register Access.................................................................................. 340
12.6.2
Conflict between Timer Counter (TCNT) Write and Increment....................... 341
12.6.3
Changing Values of CKS2 to CKS0 Bits.......................................................... 342
12.6.4
Changing Value of PSS Bit............................................................................... 342
12.6.5
Switching between Watchdog Timer Mode and Interval Timer Mode............. 342