
Rev. 1.00 Mar. 02, 2006 Page xxxiii of xl
Section 21 Power-Down Modes
Figure 21.1 Mode Transition Diagram ....................................................................................... 693
Figure 21.2 Software Standby Mode Application Example ....................................................... 696
Section 23 Electrical Characteristics
Figure 23.1 Darlington Transistor Drive Circuit (Example)....................................................... 771
Figure 23.2 LED Drive Circuit (Example) ................................................................................. 771
Figure 23.3 Output Load Circuit................................................................................................. 771
Figure 23.4 System Clock Timing.............................................................................................. 772
Figure 23.5 Oscillation Stabilization Timing.............................................................................. 773
Figure 23.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 773
Figure 23.7 Reset Input Timing.................................................................................................. 774
Figure 23.8 Interrupt Input Timing............................................................................................. 775
Figure 23.9 I/O Port Input/Output Timing.................................................................................. 777
Figure 23.10 TPU Input/Output Timing ..................................................................................... 777
Figure 23.11 TPU Clock Input Timing....................................................................................... 777
Figure 23.12 8-Bit Timer Output Timing ................................................................................... 778
Figure 23.13 8-Bit Timer Clock Input Timing ........................................................................... 778
Figure 23.14 8-Bit Timer Reset Input Timing ............................................................................ 778
Figure 23.15 PWM, PWMX Output Timing .............................................................................. 778
Figure 23.16 SCK Clock Input Timing....................................................................................... 778
Figure 23.17 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 779
Figure 23.18 PS2 Timing............................................................................................................ 780
Figure 23.19 I2C Bus Interface Input/Output Timing ................................................................. 782
Figure 23.20 LPC Interface Timing............................................................................................ 783
Figure 23.21 Test Conditions for Tester ..................................................................................... 783
Figure 23.22 JTAG ETCK Timing ............................................................................................. 784
Figure 23.23 Reset Hold Timing ................................................................................................785
Figure 23.24 JTAG Input/Output Timing................................................................................... 785
Figure 23.25 Connection of VCL Capacitor............................................................................... 788
Appendix
Figure C.1 Package Dimensions (TFP-144V) ............................................................................ 791
Figure C.2 Package Dimensions (BP-176V) .............................................................................. 792