
Rev. 1.00 Mar. 02, 2006 Page xxvii of xl
Figure 10.14 Example of Synchronous Operation Setting Procedure ........................................ 265
Figure 10.15 Example of Synchronous Operation...................................................................... 266
Figure 10.16 Compare Match Buffer Operation......................................................................... 267
Figure 10.17 Input Capture Buffer Operation............................................................................. 267
Figure 10.18 Example of Buffer Operation Setting Procedure................................................... 268
Figure 10.19 Example of Buffer Operation (1)........................................................................... 269
Figure 10.20 Example of Buffer Operation (2)........................................................................... 270
Figure 10.21 Example of PWM Mode Setting Procedure .......................................................... 272
Figure 10.22 Example of PWM Mode Operation (1) ................................................................. 273
Figure 10.23 Example of PWM Mode Operation (2) ................................................................. 273
Figure 10.24 Example of PWM Mode Operation (3) ................................................................. 274
Figure 10.25 Example of Phase Counting Mode Setting Procedure........................................... 275
Figure 10.26 Example of Phase Counting Mode 1 Operation .................................................... 276
Figure 10.27 Example of Phase Counting Mode 2 Operation .................................................... 277
Figure 10.28 Example of Phase Counting Mode 3 Operation .................................................... 278
Figure 10.29 Example of Phase Counting Mode 4 Operation .................................................... 279
Figure 10.30 Count Timing in Internal Clock Operation............................................................ 282
Figure 10.31 Count Timing in External Clock Operation........................................................... 282
Figure 10.32 Output Compare Output Timing ........................................................................... 283
Figure 10.33 Input Capture Input Signal Timing........................................................................ 283
Figure 10.34 Counter Clear Timing (Compare Match) .............................................................. 284
Figure 10.35 Counter Clear Timing (Input Capture) .................................................................. 284
Figure 10.36 Buffer Operation Timing (Compare Match).......................................................... 285
Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................. 285
Figure 10.38 TGI Interrupt Timing (Compare Match) ............................................................... 286
Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................... 286
Figure 10.40 TCIV Interrupt Setting Timing.............................................................................. 287
Figure 10.41 TCIU Interrupt Setting Timing.............................................................................. 287
Figure 10.42 Timing for Status Flag Clearing by CPU .............................................................. 288
Figure 10.43 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 289
Figure 10.44 Conflict between TCNT Write and Clear Operations ........................................... 290
Figure 10.45 Conflict between TCNT Write and Increment Operations.................................... 290
Figure 10.46 Conflict between TGR Write and Compare Match ............................................... 291
Figure 10.47 Conflict between Buffer Register Write and Compare Match............................... 292
Figure 10.48 Conflict between TGR Read and Input Capture.................................................... 292
Figure 10.49 Conflict between TGR Write and Input Capture................................................... 293
Figure 10.50 Conflict between Buffer Register Write and Input Capture .................................. 294
Figure 10.51 Conflict between Overflow and Counter Clearing ................................................ 294
Figure 10.52 Conflict between TCNT Write and Overflow ....................................................... 295