
Rev. 1.00 Mar. 02, 2006 Page xiv of xl
7.15
Port F ................................................................................................................................ 175
7.15.1
Port F Data Direction Register (PFDDR) ......................................................... 175
7.15.2
Port F Output Data Register (PFODR) ............................................................. 176
7.15.3
Port F Input Data Register (PFPIN).................................................................. 176
7.15.4
Pin Functions .................................................................................................... 177
7.15.5
Port F Nch-OD Control Register (PFNOCR) ................................................... 179
7.15.6
Pin Functions .................................................................................................... 179
7.15.7
Port F Input Pull-Up MOS................................................................................ 180
7.16
Port G................................................................................................................................ 180
7.16.1
Port G Data Direction Register (PGDDR) ........................................................ 181
7.16.2
Port G Output Data Register (PGODR)............................................................ 181
7.16.3
Port G Input Data Register (PGPIN)................................................................. 182
7.16.4
Noise Canceller Enable Register (PGNCE)...................................................... 182
7.16.5
Noise Canceller Decision Control Register (PGNCMC).................................. 183
7.16.6
Noise Cancel Cycle Setting Register (PGNCCS) ............................................. 183
7.16.7
Pin Functions .................................................................................................... 184
7.16.8
Port G Nch-OD Control Register (PGNOCR) .................................................. 187
7.16.9
Pin Functions .................................................................................................... 187
7.17
Port H................................................................................................................................ 188
7.17.1
Port H Data Direction Register (PHDDR) ........................................................ 188
7.17.2
Port H Output Data Register (PHODR)............................................................ 189
7.17.3
Port H Input Data Register (PHPIN)................................................................. 189
7.17.4
Pin Functions .................................................................................................... 190
7.17.5
Port H Nch-OD Control Register (PHNOCR) .................................................. 191
7.17.6
Pin Functions .................................................................................................... 192
7.17.7
Port H Input Pull-Up MOS ............................................................................... 192
7.18
Change of Peripheral Function Pins ................................................................................. 193
7.18.1
Port Control Register 0 (PTCNT0) ................................................................... 193
7.18.2
Port Control Register 1 (PTCNT1) ................................................................... 194
7.18.3
Port Control Register 2 (PTCNT2) ................................................................... 195
Section 8 8-Bit PWM Timer (PWM) ................................................................ 197
8.1
Features............................................................................................................................. 197
8.2
Pin Configuration.............................................................................................................. 199
8.3
Register Descriptions........................................................................................................ 199
8.3.1
PWM Register Select (PWSL).......................................................................... 200
8.3.2
PWM Clock Select Register (PWCSR) ............................................................ 201
8.3.3
PWM Data Registers 7 to 0 (PWDR7 to PWDR0)........................................... 204
8.3.4
PWM Data Polarity Register (PWDPR) ........................................................... 204
8.3.5
PWM Output Enable Register (PWOER) ......................................................... 205