
Rev. 1.00 Mar. 02, 2006 Page xxxviii of xl
Table 13.6
BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 362
Table 13.7
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 363
Table 13.8
BRR Settings for Various Bit Rates
(Smart Card Interface Mode, n = 0, s = 372) ........................................................ 363
Table 13.9
Maximum Bit Rate for Each Frequency
(Smart Card Interface Mode, S = 372).................................................................. 363
Table 13.10
Serial Transfer Formats (Asynchronous Mode)................................................ 365
Table 13.11
SSR Status Flags and Receive Data Handling .................................................. 372
Table 13.12
SCI Interrupt Sources........................................................................................ 400
Table 13.13
SCI Interrupt Sources........................................................................................ 401
Section 14 I2C Bus Interface (IIC)
Table 14.1
Pin Configuration.................................................................................................. 410
Table 14.2
Communication Format ........................................................................................ 414
Table 14.3
I2C Transfer Rate .................................................................................................. 417
Table 14.4
Flags and Transfer States (Master Mode)............................................................. 423
Table 14.5
Flags and Transfer States (Slave Mode) ............................................................... 425
Table 14.6
I2C Bus Data Format Symbols.............................................................................. 437
Table 14.7
IIC Interrupt Sources ............................................................................................ 465
Table 14.8
I2C Bus Timing (SCL and SDA Outputs)............................................................. 466
Table 14.9
Permissible SCL Rise Time (tsr) Values ............................................................... 467
Table 14.10
I2C Bus Timing (with Maximum Influence of tSr/tSf)........................................ 468
Section 15 Keyboard Buffer Control Unit (PS2)
Table 15.1
Pin Configuration.................................................................................................. 482
Section 16 LPC Interface (LPC)
Table 16.1
Pin Configuration.................................................................................................. 509
Table 16.2
LPC I/O Cycle ...................................................................................................... 551
Table 16.3
GA20 Setting/Clearing Timing............................................................................. 553
Table 16.4
Fast Gate A20 Output Signals............................................................................... 555
Table 16.5
Scope of LPC Interface Pin Shutdown ................................................................. 557
Table 16.6
Scope of Initialization in Each LPC interface Mode ............................................ 558
Table 16.7
Serialized Interrupt Transfer Cycle Frame Configuration .................................... 561
Table 16.8
Receive Complete Interrupts and Error Interrupt.................................................. 563
Table 16.9
HIRQ Setting and Clearing Conditions ................................................................ 564
Table 16.10
Host Address Example...................................................................................... 567
Section 17 A/D Converter
Table 17.1
Pin Configuration.................................................................................................. 571
Table 17.2
Analog Input Channels and Corresponding ADDR.............................................. 572
Table 17.3
A/D Conversion Time (Single Mode)................................................................... 578