
Section 1 Overview
Rev. 1.00 Mar. 02, 2006 Page 3 of 798
REJ09B0255-0100
1.2
Internal Block Diagram
PA0/
KIN8/PS2DC
PA1/
KIN9/PS2DD
PA2/
KIN10/PS2AC
PA3/
KIN11/PS2AD
PA4/
KIN12/PS2BC
PA5/
KIN13/PS2BD
PA6/
KIN14/PS2CC
PA7/
KIN15/PS2CD
P20
P21
P22
P23
P24
P25
P26
P27
P10
P11
P12
P13
P14
P15
P16
P17
P30/LAD0
P31/LAD1
P32/LAD2
P33/LAD3
P34/
LFRAME
P35/
LRESET
P36/LCLK
P37/SERIRQ
PB0/
LSMI
PB1/LSCI
PB2
PB3
PB4
PB5
PB6
PB7
PC0/TIOCA0/
WUE8
PC1/TIOCB0/
WUE9
PC2/TIOCC0/TCLKA/
WUE10
PC3/TIOCD0/TCLKB/
WUE11
PC4/TIOCA1/
WUE12
PC5/TIOCB1/TCLKC/
WUE13
PC6/TIOCA2/
WUE14
PC7/TIOCB2/TCLKD/
WUE15
P50
P51
P52/SCL0
PF0/PWM2/
IRQ8
PF1/PWM3/
IRQ9
PF2/TMOY/
IRQ10
PF3/TMOX/
IRQ11
PF4/PWM4
PF5/PWM5
PF6/PWM6
PF7/PWM7
RAM
WDT
(2 channels)
PS2
(4 channels)
8-bit timer
(4 channels)
IIC
(3 channels)
10-bit A/D converter
(16 channels)
SCI
(1 channel)
Smart Card I/F
(1 channel)
8-bit PWM
(8 channels)
14-bit PWM
(2 channels)
LPC
(4 channels)
16-bit TPU
(3 channels)
Interrupt
controller
Port
H
Port
E
Port
9
Port
6
Port
4
Port
8
Port
F
Port 7
Port D
Port G
Port
C
Port
5
Port
B
Port
3
Port
1
Port
2
Port
A
B
us
con
tro
ller
Clock pulse
generator
ROM
(flash memory)
H8S/2000CPU
RES
XTAL
EXTAL
MD2
MD1
NMI
ETRST
VCC
VCL
VSS
A
Vref
A
VCC
A
VSS
H-UDI
P80/
PME
P81/GA20
P82/
CLKRUN
P83/
LPCPD
P84/
IRQ3/TxD1
P85/
IRQ4/RxD1
P86/
IRQ5/SCK1/SCL1
P40/TMI0
P41/TMO0
P42/SDA1
P43/TMI1/ExSCK1
P44/TMO1
P45
P46/PWX0/PWM0
P47/PWX1/PWM1
P60/
KIN0
P61/
KIN1
P62/
KIN2
P63/
KIN3
P64/
KIN4
P65/
KIN5
P66/
IRQ6/KIN6
P67/
IRQ7/KIN7
P90/
IRQ2
P91/
IRQ1
P92/
IRQ0
P93/
IRQ12
P94/
IRQ13
P95/
IRQ14
P96/
φ/EXCL
P97/SDA0/
IRQ15
PE0
PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS
PH0/
ExIRQ6
PH1/
ExIRQ7
PH2/FWE
PH3/ExEXCL
PH4
PH5
PG0/
ExIRQ8
/TMIX
PG1/
ExIRQ9
/TMIY
PG2/
ExIRQ10
/SDA2
PG3/
ExIRQ11
/SCL2
PG4/
ExIRQ12
/ExSDAA
PG5/
ExIRQ13
/ExSCLA
PG6/
ExIRQ14
/ExSDAB
PG7/
ExIRQ15
/ExSCLB
PD0/AN8
PD1/AN9
PD2AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
Internal
addr
ess
b
us
Internal
d
ata
b
us
Address
b
us
D
ata
bu
s
Note: * Not supported by the system development tool (emulator)
Figure 1.1 H8S/2116 Group Internal Block Diagram