
Rev. 1.00 Mar. 02, 2006 Page xxi of xl
16.3.9
Input Data Registers 1 to 4 (IDR1 to IDR4) ..................................................... 528
16.3.10
Output Data Registers 1 to 4 (ODR1 to ODR4)................................................ 528
16.3.11
Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) ................................. 529
16.3.12
Status Registers 1 to 4 (STR1 to STR4) ........................................................... 529
16.3.13
SERIRQ Control Register 0 (SIRQCR0).......................................................... 536
16.3.14
SERIRQ Control Register 1 (SIRQCR1).......................................................... 540
16.3.15
SERIRQ Control Register 2 (SIRQCR2).......................................................... 544
16.3.16
SERIRQ Control Register 3 (SIRQCR3).......................................................... 548
16.3.17
Host Interface Select Register (HISEL)............................................................ 549
16.4
Operation .......................................................................................................................... 550
16.4.1
LPC interface Activation .................................................................................. 550
16.4.2
LPC I/O Cycles ................................................................................................. 550
16.4.3
Gate A20 ........................................................................................................... 553
16.4.4
LPC Interface Shutdown Function (LPCPD).................................................... 556
16.4.5
LPC Interface Serialized Interrupt Operation (SERIRQ).................................. 560
16.4.6
LPC Interface Clock Start Request ................................................................... 562
16.5
Interrupt Sources...............................................................................................................563
16.5.1
IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI ................................................. 563
16.5.2
SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 .................... 563
16.6
Usage Note........................................................................................................................ 566
16.6.1
Data Conflict..................................................................................................... 566
Section 17 A/D Converter..................................................................................569
17.1
Features............................................................................................................................. 569
17.2
Input/Output Pins .............................................................................................................. 571
17.3
Register Descriptions ........................................................................................................ 572
17.3.1
A/D Data Registers A to H (ADDRA to ADDRH) .......................................... 572
17.3.2
A/D Control/Status Register (ADCSR) ............................................................ 573
17.3.3
A/D Control Register (ADCR) ......................................................................... 575
17.4
Operation .......................................................................................................................... 576
17.4.1
Single Mode...................................................................................................... 576
17.4.2
Scan Mode ........................................................................................................ 577
17.4.3
Input Sampling and A/D Conversion Time ...................................................... 577
17.5
Interrupt Source ................................................................................................................579
17.6
A/D Conversion Accuracy Definitions ............................................................................. 579
17.7
Usage Notes ...................................................................................................................... 581
17.7.1
Module Stop Mode Setting ............................................................................... 581
17.7.2
Permissible Signal Source Impedance .............................................................. 581
17.7.3
Influences on Absolute Accuracy ..................................................................... 582
17.7.4
Setting Range of Analog Power Supply and Other Pins ................................... 582