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型號(hào)：	R4F2116BG20V
元件分類(lèi)：	微控制器/微處理器
英文描述：	16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PBGA176
封裝：	13 X 13 MM, 0.80 MM PITCH, PLASTIC, LFBGA-176
文件頁(yè)數(shù)：	576/842頁(yè)
文件大小：	5188K
代理商：	R4F2116BG20V

Section 17 A/D Converter

Rev. 1.00 Mar. 02, 2006 Page 577 of 798

REJ09B0255-0100

Scan Mode

In scan mode, A/D conversion is performed sequentially on the specified channels (max. four

channels or eight channels). Operations are as follows.

1. When the ADST bit in ADCSR is set to 1 by software, TPU, or an external trigger input, A/D

conversion starts on the first channel in the selected channel set.

Continuous A/D conversion on up to four channels (SCANE

= 1 and SCANS = 0) or

continuous A/D conversion on up to eight channels (SCANE

= 1 and SCANS = 1) can be

selected. When continuous A/D conversion on four channels is selected, A/D conversion starts

from the following channels: AN0 when CH3

= 0 and CH2 = 0, AN4 when CH3 = 0 and CH2

= 1, AN8 when CH3 = 1 and CH2 = 0, and AN12 when CH3 = 1 and CH2 = 1.

When continuous A/D conversion on eight channels is selected, A/D conversion starts from

the following channels: AN0 when CH3

= 0 and CH2 = 0 and AN8 when CH3 = 1 and CH2 =

2. When A/D conversion for each channel is completed, the result is sequentially transferred to

the A/D data register corresponding to each channel.

3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.

If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion from the first

channel in the channel set starts again.

4. The ADST bit is not automatically cleared to 0 so steps [2] and [3] are repeated as long as the

ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the

A/D converter enters wait state. After this, setting the ADST bit to 1 starts A/D conversion

from the first channel again.

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input when the A/D conversion start delay time (t

D) passes after the ADST bit in ADCSR is set to

1, then starts A/D conversion. Figure 17.2 shows the A/D conversion timing. Table 17.3 indicates

the A/D conversion time.

As indicated in figure 17.2, the A/D conversion time (t

CONV) includes tD and the input sampling time

SPL). The length of tD varies depending on the timing of write to ADCSR. The total conversion

time therefore varies within the ranges indicated in table 17.3.

In scan mode, the values shown in table 17.3 become those for the first conversion time. The

second and subsequent conversion times are listed in table 17.4. The setting that makes for the

conversion time of 134 states should only be used when the system clock (

φ) is 16 MHz or less.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
R4F2116VBG20V	制造商:Renesas Electronics Corporation 功能描述:MCU 3V 128K,PB-FREE 176-BGA - Trays
R4F2117VBG	制造商:Renesas Electronics Corporation 功能描述:
R4F2117VBG20V	制造商:Renesas Electronics Corporation 功能描述:
R4F2117VLP	制造商:Renesas Electronics Corporation 功能描述:
R4F2117VTE	制造商:Renesas Electronics Corporation 功能描述:MCU, FLASH, 20MHZ, 3.0 TO 3.6V - Trays

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