
Rev. 1.00 Mar. 02, 2006 Page xxix of xl
Figure 13.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)........................................... 376
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 377
Figure 13.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 378
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 379
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 380
Figure 13.14 Data Format in Synchronous Communication (LSB-First)................................... 381
Figure 13.15 Sample SCI Initialization Flowchart ..................................................................... 382
Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode .................. 384
Figure 13.17 Sample Serial Transmission Flowchart ................................................................. 384
Figure 13.18 Example of SCI Receive Operation in Clocked Synchronous Mode .................... 385
Figure 13.19 Sample Serial Reception Flowchart ...................................................................... 386
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 388
Figure 13.21 Pin Connection for Smart Card Interface .............................................................. 389
Figure 13.22 Data Formats in Normal Smart Card Interface Mode............................................ 390
Figure 13.23 Direct Convention (SDIR = SINV = O/
E = 0) ......................................................390
Figure 13.24 Inverse Convention (SDIR = SINV = O/
E = 1).....................................................391
Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency is 372 Times the Bit Rate) ............................................. 392
Figure 13.26 Data Re-transfer Operation in SCI Transmission Mode........................................ 394
Figure 13.27 TEND Flag Set Timings during Transmission ...................................................... 394
Figure 13.28 Sample Transmission Flowchart ........................................................................... 395
Figure 13.29 Data Re-transfer Operation in SCI Reception Mode ............................................. 396
Figure 13.30 Sample Reception Flowchart................................................................................. 397
Figure 13.31 Clock Output Fixing Timing ................................................................................. 398
Figure 13.32 Clock Stop and Restart Procedure ......................................................................... 399
Figure 13.33 Sample Flowchart for Mode Transition during Transmission............................... 403
Figure 13.34 Pin States during Transmission in Asynchronous Mode (Internal Clock)............. 404
Figure 13.35 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock)...................................................................................................... 404
Figure 13.36 Sample Flowchart for Mode Transition during Reception .................................... 405
Figure 13.37 Switching from SCK Pins to Port Pins.................................................................. 406
Figure 13.38 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins.......... 406
Section 14 I2C Bus Interface (IIC)
Figure 14.1 Block Diagram of I2C Bus Interface........................................................................ 408
Figure 14.2 I2C Bus Interface Connections (Example: This LSI as Master) .............................. 409
Figure 14.3 I2C Bus Data Format (I2C Bus Format)................................................................... 436
Figure 14.4 I2C Bus Data Format (Serial Format) ...................................................................... 436
Figure 14.5 I2C Bus Timing........................................................................................................ 437