
Section 16 LPC Interface (LPC)
Rev. 1.00 Mar. 02, 2006 Page 528 of 798
REJ09B0255-0100
Host select register
I/O Address
Bits 5 to 3
Bit 2
Bits 1 and 0
Transfer
Cycle
Host Select Register
Bits 15 to 3 in LADR4
0
Bits 1 and 0 in LADR4
I/O write
IDR4 write (data)
Bits 15 to 3 in LADR4
1
Bits 1 and 0 in LADR4
I/O write
IDR4 write (command)
Bits 15 to 3 in LADR4
0
Bits 1 and 0 in LADR4
I/O read
ODR4 read
Bits 15 to 3 in LADR4
1
Bits 1 and 0 in LADR4
I/O read
STR4 read
Note:
*
When channel 4 is used, the content of LADR4 must be set so that the addresses for
channels 1, 2, and 3 are different.
16.3.9
Input Data Registers 1 to 4 (IDR1 to IDR4)
IDR1 to IDR4 are 8-bit read-only registers for the slave (this LSI), and 8-bit write-only registers
for the host. The registers selected from the host according to the I/O address are shown in the
following table. For information on IDR3 and IDR4 selection, see the section of the corresponding
LADR. Data transferred in an LPC I/O write cycle is written to the selected register. The value of
bit 2 of the I/O address is latched into the C/
D bit in STR, to indicate whether the written
information is a command or data. The initial values of IDR1 to IDR4 are undefined.
I/O Address
Bits 15 to 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register Selection
Bits 15 to 4
Bit 3
0
Bit 1
Bit 0
I/O write
IDRn write, C/
Dn ← 0
Bits 15 to 4
Bit 3
1
Bit 1
Bit 0
I/O write
IDRn write, C/
Dn ← 1
n = 1 to 4
16.3.10
Output Data Registers 1 to 4 (ODR1 to ODR4)
ODR1 to ODR4 are 8-bit readable/writable registers for the slave (this LSI), and 8-bit read-only
registers for the host. The registers selected from the host according to the I/O address are shown
in the following table. For information on ODR3 and ODR4 selection, see the section of the
corresponding LADR. In an LPC I/O read cycle, the data in the selected register is transferred to
the host. The initial values of ODR1 to ODR4 are undefined.
I/O Address
Bits 15 to 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register Selection
Bits 15 to 4
Bit 3
0
Bit1
Bit 0
I/O read
ODRn read
n = 1 to 4