
Rev. 1.00 Mar. 02, 2006 Page xxxv of xl
Tables
Section 1 Overview
Table 1.1
H8S/2116 Group Pin Arrangement in Each Operating Mode................................... 6
Table 1.2
Pin Functions .......................................................................................................... 11
Section 2 CPU
Table 2.1
Instruction Classification ........................................................................................ 35
Table 2.2
Operation Notation ................................................................................................. 36
Table 2.3
Data Transfer Instructions....................................................................................... 37
Table 2.4
Arithmetic Operations Instructions (1) ................................................................... 38
Table 2.4
Arithmetic Operations Instructions (2) ................................................................... 39
Table 2.5
Logic Operations Instructions................................................................................. 40
Table 2.6
Shift Instructions..................................................................................................... 40
Table 2.7
Bit Manipulation Instructions (1)............................................................................ 41
Table 2.7
Bit Manipulation Instructions (2)............................................................................ 42
Table 2.8
Branch Instructions ................................................................................................. 43
Table 2.9
System Control Instructions.................................................................................... 44
Table 2.10
Block Data Transfer Instructions ............................................................................ 45
Table 2.11
Addressing Modes .................................................................................................. 47
Table 2.12
Absolute Address Access Ranges ........................................................................... 49
Table 2.13
Effective Address Calculation (1)........................................................................... 51
Table 2.13
Effective Address Calculation (2)........................................................................... 52
Section 3 MCU Operating Modes
Table 3.1
MCU Operating Mode Selection ............................................................................ 57
Section 4 Exception Handling
Table 4.1
Exception Types and Priority.................................................................................. 65
Table 4.2
Exception Handling Vector Table
(H8S/2140B Group Compatible Vector Mode) ...................................................... 66
Table 4.3
Exception Handling Vector Table (Extended Vector Mode).................................. 68
Table 4.4
Status of CCR after Trap Instruction Exception Handling ..................................... 71
Section 5 Interrupt Controller
Table 5.1
Pin Configuration.................................................................................................... 77
Table 5.2
Correspondence between Interrupt Source and ICR
(H8S/2140B Group Compatible Vector Mode: EIVS = 0) ..................................... 79
Table 5.3
Correspondence between Interrupt Source and ICR
(Extended Vector Mode: EIVS = 1) ....................................................................... 79