
Section 14 I2C Bus Interface (IIC)
Rev. 1.00 Mar. 02, 2006 Page 468 of 798
REJ09B0255-0100
Table 14.10 I
2C Bus Timing (with Maximum Influence of t
Sr/tSf)
Time Indication (at Maximum Transfer Rate) [ns]
Item
t
cyc Indication
t
Sr/tSf
Influence
(Max.)
I
2C Bus
Specifi-cation
(Min.)
φ =
8 MHz
φ =
10 MHz
φ =
16 MHz
φ =
20 MHz
Standard mode
–1000
4000
t
SCLHO
0.5 t
SCLO (–tSr)
High-speed mode –300
600
950
Standard mode
–250
4700
4750
t
SCLLO
0.5 t
SCLO (–tSf)
High-speed mode –250
1300
1000*
1
1000*
1
1000*
1
1000*
1
Standard mode
–1000
4700
3875*
1
3900*
1
3939*
1
3950*
1
t
BUFO
0.5 t
SCLO –1 tcyc
(–t
Sr)
High-speed mode –300
1300
825*
1
850*
1
888*
1
900*
1
Standard mode
–250
4000
4625
4650
4688
4700
t
STAHO
0.5 t
SCLO –1 tcyc
(–t
Sf)
High-speed mode –250
600
875
900
938
900
Standard mode
–1000
4700
9000
t
STASO
1 t
SCLO (–tSr)
High-speed mode –300
600
2200
Standard mode
–1000
4000
4250
4200
4125
4100
t
STOSO
0.5 t
SCLO + 2 tcyc
(–t
Sr)
High-speed mode –300
600
1200
1150
1075
1050
Standard mode
–1000
250
3325
3400
3513
3550
t
SDASO
(master)
1 t
SCLLO*
3 –3 t
cyc
(–t
Sr)
High-speed mode –300
100
625
700
813
850
Standard mode
–1000
250
2200
2500
2950
3100
t
SDASO
(slave)
1 t
SCLL*
3
–12 t
cyc*
2
(–t
Sr)
High-speed mode –300
100
–500*
1
–200*
1
250
400
Standard mode
0
375
300
188
150
t
SDAHO
3 t
cyc
High-speed mode 0
0
375
300
188
150
Notes: 1. Does not meet the I
2C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I
2C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t
SCLL –
6 t
cyc).
3. Calculated using the I
2C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).